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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. advance information for pre-production products; subject to change without notice. ads122u04 sbas752 ? may 2017 ads122u04 24-bit, 4-channel, 2-ksps, delta-sigma adc with uart interface 1 1 features 1 ? current consumption as low as 315 a (typ) ? wide supply range: 2.3 v to 5.5 v ? programmable gain: 1 to 128 ? programmable data rates: up to 2 ksps ? up to 20-bits effective resolution ? simultaneous 50-hz and 60-hz rejection at 20 sps with single-cycle settling digital filter ? two differential or four single-ended inputs ? dual-matched programmable current sources: 10 a to 1.5 ma ? internal 2.048-v reference: 5 ppm/ c (typ) drift ? internal 2% accurate oscillator ? internal temperature sensor: 0.5 c (typ) accuracy ? three general-purpose inputs/outputs ? 2-wire uart compatible interface (8-n-1 format) with baud rates up to 120 kbaud and auto- baud-rate detection ? package: 3.0-mm 3.0-mm 0.75-mm wqfn 2 applications ? temperature sensor measurements: ? thermistors ? thermocouples ? resistance temperature detectors (rtds): 2-, 3-, or 4-wire types ? resistive bridge sensor measurements: ? pressure sensors ? strain gauges ? weigh scales 3 description the ads122u04 is a precision, 24-bit, analog-to- digital converter (adc) that offers many integrated features to reduce system cost and component count in applications measuring small sensor signals. the device features two differential or four single-ended inputs through a flexible input multiplexer (mux), a low-noise, programmable gain amplifier (pga), two programmable excitation current sources, a voltage reference, an oscillator, and a precision temperature sensor. the device can perform conversions at data rates up to 2000 samples-per-second (sps) with single-cycle settling. at 20 sps, the digital filter offers simultaneous 50-hz and 60-hz rejection for noisy industrial applications. the internal pga offers gains up to 128. this pga makes the ads122u04 ideally suited for applications measuring small sensor signals, such as resistance temperature detectors (rtds), thermocouples, thermistors, and resistive bridge sensors. the ads122u04 features a 2-wire, uart-compatible interface. in applications that require galvanic isolation this universal asynchronous receiver/transmitter (uart) interface minimizes the number of digital isolation channels, thus saving cost, board space, and power. the ads122u04 is offered in a leadless 16-pin wqfn or a 16-pin tssop package and is specified over a temperature range of ? 40 c to +125 c. device information (1) part number package body size (nom) ads122u04 wqfn (16) 3.00 mm 3.00 mm tssop (16) 5.00 mm 4.40 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. k-type thermocouple measurement advance information 3.3 v 3.3 v thermocouple 0.1 f 3.3 v 0.1 f reference mux precision temperature sensor ain0 ain1 ain2 ain3 rx tx avdd avss gpio1 gpio0 ads122u04 dgnd refp refn 2.048-v reference 10 a to 1.5 ma mux dvdd pga 24-bit ? adc digital filter and uart interface isothermal block low drift oscillator gpio2/ reset drdy copyright ? 2017, texas instruments incorporated productfolder ordernow technical documents tools & software support &community
2 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 device family comparison table ........................ 3 6 pin configuration and functions ......................... 4 7 specifications ......................................................... 5 7.1 absolute maximum ratings ...................................... 5 7.2 esd ratings .............................................................. 5 7.3 recommended operating conditions ....................... 5 7.4 thermal information .................................................. 6 7.5 electrical characteristics ........................................... 6 7.6 uart timing requirements ..................................... 9 7.7 uart switching characteristics ............................... 9 8 parameter measurement information ................ 11 8.1 noise performance ................................................. 11 9 detailed description ............................................ 14 9.1 overview ................................................................. 14 9.2 functional block diagram ....................................... 14 9.3 feature description ................................................. 15 9.4 device functional modes ........................................ 26 9.5 programming ........................................................... 29 9.6 register map ........................................................... 35 10 application and implementation ........................ 41 10.1 application information .......................................... 41 10.2 typical applications .............................................. 46 11 power supply recommendations ..................... 56 11.1 power-supply sequencing .................................... 56 11.2 power-supply ramp rate .................................... 56 11.3 power-supply decoupling ..................................... 56 12 layout ................................................................... 57 12.1 layout guidelines ................................................. 57 12.2 layout example .................................................... 58 13 device and documentation support ................. 59 13.1 documentation support ........................................ 59 13.2 receiving notification of documentation updates 59 13.3 community resources .......................................... 59 13.4 trademarks ........................................................... 59 13.5 electrostatic discharge caution ............................ 59 13.6 glossary ................................................................ 59 14 mechanical, packaging, and orderable information ........................................................... 59 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. date revision notes may 2017 * initial release. advance information
3 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 5 device family comparison table device resolution (bits) interface max data rate (ksps) excitation current sources gpios temperature sensor bipolar supply clock low-side switch ads1120 16 spi 2 yes 0 yes yes internal, external yes ads1220 24 spi 2 yes 0 yes yes internal, external yes ads112u04 16 uart 2 yes 3 yes yes internal no ads122u04 24 uart 2 yes 3 yes yes internal no advance information
4 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 6 pin configuration and functions rte package 16-pin wqfn top view pw package 16-pin tssop top view (1) see the unused inputs and outputs section for details on how to connect unused pins. pin functions pin analog or digital input/output description (1) name no. rte pw ain0 9 11 analog input analog input 0 ain1 8 10 analog input analog input 1 ain2 5 7 analog input analog input 2 ain3 4 6 analog input analog input 3 avdd 10 12 analog supply positive analog power supply. connect a 100-nf (or larger) capacitor to avss. avss 3 5 analog supply negative analog power supply dgnd 2 4 digital supply digital ground dvdd 11 13 digital supply positive digital power supply. connect a 100-nf (or larger) capacitor to dgnd. gpio0 16 2 digital input/output general-purpose input/output 0 gpio1 15 1 digital input/output general-purpose input/output 1 gpio2/ drdy 12 14 digital input/output general-purpose input/output 2 or data ready; active low. refn 6 8 analog input negative reference input refp 7 9 analog input positive reference input reset 1 3 digital input reset; active low rx 14 16 digital input receive tx 13 15 digital output transmit thermal pad pad ? ? thermal power pad. do not connect or only connect to avss. advance information 16 gpio0 5 ain2 1 reset 12 gpio2/drdy 15 gpio1 6 refn 2 dgnd 11 dvdd 14 rx 7 refp 3 avss 10 avdd 13 tx 8 ain1 4 ain3 9 ain0 not to scale thermal pad 1 gpio1 16 rx 2 gpio0 15 tx 3 reset 14 gpio2/drdy 4 dgnd 13 dvdd 5 avss 12 avdd 6 ain3 11 ain0 7 ain2 10 ain1 8 refn 9 refp not to scale
5 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7 specifications 7.1 absolute maximum ratings (1) min max unit power-supply voltage avdd to avss ? 0.3 7 v dvdd to dgnd ? 0.3 7 avss to dgnd ? 2.8 0.3 analog input voltage ain0, ain1, ain2, ain3, refp, refn avss ? 0.3 avdd + 0.3 v digital input voltage tx, rx, gpio0, gpio1, gpio2/ drdy, reset dgnd ? 0.3 dvdd + 0.3 v input current continuous, any pin except power-supply pins ? 10 10 ma temperature junction, t j 150 c storage, t stg ? 60 150 (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 7.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged-device model (cdm), per jedec specification jesd22-c101 (2) 500 (1) ain p and ain n denote the positive and negative inputs of the pga. ainx denotes one of the four available analog inputs. pga disabled means the low-noise pga is powered down and bypassed. gains of 1, 2, and 4 are still possible in this case. see the low-noise programmable gain stage section for more information. (2) v inmax denotes the maximum differential input voltage, v in , that is expected in the application. |v inmax | can be smaller than v ref / gain. (3) excluding the effects of offset and gain error. 7.3 recommended operating conditions over operating ambient temperature range (unless otherwise noted) min nom max unit power supply unipolar analog power supply avdd to avss 2.3 5.5 v avss to dgnd ? 0.1 0 0.1 bipolar analog power supply avdd to dgnd 2.3 2.5 2.75 v avss to dgnd ? 2.75 ? 2.5 ? 2.3 digital power supply dvdd to dgnd 2.3 5.5 v analog inputs (1) v (ainx) absolute input voltage (2) pga disabled, gain = 1 to 4 avss ? 0.1 avdd + 0.1 v pga enabled, gain = 1 to 4 avss + 0.2 avdd ? 0.2 pga enabled, gain = 8 to 128 avss + 0.2 + |v inmax | (gain ? 4) / 8 avdd ? 0.2 ? |v inmax | (gain ? 4) / 8 v in differential input voltage v in = v ainp ? v ainn (3) ? v ref / gain v ref / gain v voltage reference inputs v ref differential reference input voltage v ref = v (refp) ? v (refn) 0.75 2.5 avdd ? avss v v (refn) absolute negative reference voltage avss ? 0.1 v (refp) ? 0.75 v v (refp) absolute positive reference voltage v (refn) + 0.75 avdd + 0.1 v digital inputs input voltage rx, gpio0, gpio1, gpio2/ drdy, reset dgnd dvdd v temperature range t a operating ambient temperature ? 40 125 c advance information
6 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 7.4 thermal information thermal metric (1) ads122u04 unit wqfn (rte) tssop (pw) 16 pins 16 pins r ja junction-to-ambient thermal resistance 57.7 90.3 c/w r jc(top) junction-to-case (top) thermal resistance 29.0 31.7 c/w r jb junction-to-board thermal resistance 19.9 41.8 c/w jt junction-to-top characterization parameter 0.3 1.8 c/w jb junction-to-board characterization parameter 19.8 41.2 c/w r jc(bot) junction-to-case (bottom) thermal resistance 11.8 n/a c/w (1) see the noise performance section for more information. 7.5 electrical characteristics minimum and maximum specifications apply from t a = ? 40 c to +125 c; typical specifications are at t a = 25 c; all specifications are at avdd = 2.3 v to 5.5 v, avss = 0 v, dvdd = 3.3 v, pga enabled, all data rates, and internal reference enabled (unless otherwise noted) parameter test conditions min typ max unit analog inputs absolute input current pga disabled, gain = 1 to 4 tbd na gain = 1 to 128, v (ainx)min v (ainx) v (ainx)max tbd absolute input current drift pga disabled, gain = 1 to 4 tbd pa/ c gain = 1 to 128, v (ainx)min v (ainx) v (ainx)max tbd differential input current pga disabled, gain = 1 to 4, v cm = avdd / 2, ? v ref / gain v in v ref / gain tbd na/v gain = 1 to 128, v cm = avdd / 2, ? v ref / gain v in v ref / gain tbd na differential input current drift pga disabled, gain = 1 to 4, v cm = avdd / 2, ? v ref / gain v in v ref / gain tbd pa/ c gain = 1 to 128, v cm = avdd / 2, ? v ref / gain v in v ref / gain tbd system performance resolution (no missing codes) 24 bits dr data rate normal mode 20, 45, 90, 175, 330, 600, 1000 sps turbo mode 40, 90, 180, 350, 660, 1200, 2000 noise (input-referred) (1) normal mode, gain = 128, dr = 20 sps tbd nv rms inl integral nonlinearity avdd = 3.3 v, gain = 1 to 128, v cm = 0.5 avdd, external v ref , normal mode, best fit ? 15 6 15 ppm fsr v io input offset voltage pga disabled, gain = 1 to 4, differential inputs 4 v gain = 1, differential inputs, t a = 25 c ? 30 4 30 gain = 2 to 128, differential inputs 4 offset drift pga disabled, gain = 1 to 4 0.25 v/ c gain = 1 to 128, t a = ? 40 c to +85 c 0.08 0.3 gain = 1 to 128 0.25 tbd offset match match between any two inputs (at the same gain setting tbd?) 20 v gain error pga disabled, gain = 1 to 4 0.015% gain = 1 to 128, t a = 25 c ? 0.1% 0.015% 0.1% gain drift pga disabled, gain = 1 to 4 1 ppm/ c gain = 1 to 128, t a = ? 40 c to +85 c tbd tbd gain = 1 to 128 1 4 advance information
7 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) minimum and maximum specifications apply from t a = ? 40 c to +125 c; typical specifications are at t a = 25 c; all specifications are at avdd = 2.3 v to 5.5 v, avss = 0 v, dvdd = 3.3 v, pga enabled, all data rates, and internal reference enabled (unless otherwise noted) parameter test conditions min typ max unit system performance (continued) nmrr normal-mode rejection ratio 50 hz 1 hz, dr = 20 sps 78 88 db 60 hz 1 hz, dr = 20 sps 80 88 cmrr common-mode rejection ratio at dc, gain = 1 90 105 db f cm = 50 hz, dr = 20 sps tbd tbd f cm = 50 hz, dr = 2000 sps 95 115 f cm = 60 hz, dr = 20 sps tbd tbd f cm = 60 hz, dr = 2000 sps 95 115 psrr power-supply rejection ratio avdd at dc (v cm = 0.5 avdd, gain = 1 tbd) 80 105 db avdd at 50 hz or 60 hz (v cm = 0.5 avdd, gain = 1 tbd) tbd tbd dvdd at dc (v cm = 0.5 avdd, gain = 1 tbd) 100 115 internal voltage reference v ref reference voltage 2.048 v accuracy t a = 25 c ? 0.15% tbd 0.15% temperature drift t a = ? 40 c to +85 c tbd tbd ppm/ c 5 30 long-term drift 1000 hours 110 ppm voltage reference inputs reference input current refp = v ref , refn = avss 10 na internal oscillator f clk frequency normal mode 1.024 mhz turbo mode 2.048 accuracy normal mode ? 2% 1% 2% excitation current sources (idacs) (avdd = 3.3 v to 5.5 v) current settings 10, 50, 100, 250, 500, 1000, 1500 a compliance voltage all current settings, 0.1% (tbd) deviation avdd ? 0.9 v accuracy all current settings, each idac ? 6% 1% 6% current matching between idacs (not valid for 10- a setting) 0.3% tbd temperature drift each idac (not valid for 10- a setting) 50 ppm/ c temperature drift matching between idacs (not valid for 10- a setting) 10 tbd ppm/ c burn-out current sources (bocs) magnitude sink and source 10 a accuracy tbd% temperature sensor conversion resolution 14 bits temperature resolution 0.03125 c accuracy t a = 0 c to +75 c ? 0.5 0.25 0.5 c t a = ? 40 c to +125 c ? 1 0.5 1 accuracy vs analog supply voltage 0.0625 0.25 c/v digital inputs/outputs v il logic input level, low dgnd 0.3 dvdd v v ih logic input level, high 0.7 dvdd dvdd v v ol logic output level, low i ol = 1 ma 0.2 dvdd v v oh logic output level, high i oh = 1 ma 0.8 dvdd v input current dgnd v digital input dvdd ? 1 1 a advance information
8 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) minimum and maximum specifications apply from t a = ? 40 c to +125 c; typical specifications are at t a = 25 c; all specifications are at avdd = 2.3 v to 5.5 v, avss = 0 v, dvdd = 3.3 v, pga enabled, all data rates, and internal reference enabled (unless otherwise noted) parameter test conditions min typ max unit analog supply current (avdd = 3.3 v, v in = 0 v, idacs turned off) i avdd analog supply current power-down mode 0.1 3 a normal mode, pga disabled, gain = 1 to 4 240 normal mode, gain = 1 to 16 340 490 normal mode, gain = 32 425 normal mode, gain = 64, 128 510 turbo mode, pga disabled, gain = 1 to 4 360 turbo mode, gain = 1 to 16 540 turbo mode, gain = 32 715 turbo mode, gain = 64, 128 890 additional analog supply currents per function (avdd = 3.3 v) i avdd analog supply current external reference selected 70 a idac overhead (excludes the actual idac current) 190 digital supply current (dvdd = 3.3 v, all data rates, spi not active) i dvdd digital supply current power-down mode 0.3 5 a normal mode 75 110 turbo mode 95 power dissipation (avdd = dvdd = 3.3 v, all data rates, v in = 0 v, spi not active) p d power dissipation normal mode, gain = 1 to 16 1.4 mw turbo mode, gain = 1 to 16 2.1 advance information
9 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) the uart baud rate affects the command latch timing; see the command latching section for more details. (2) see the timeout section for more information. t mod = 1 / f mod . modulator frequency f mod = 256 khz (normal mode) and 512 khz (turbo mode). 7.6 uart timing requirements over operating ambient temperature range and dvdd = 2.3 v to 5.5 v (unless otherwise noted) min typ max unit 1/t baud bus baud rate 2 120 kbaud t r(rx) rise time 10-pf load 15 % of t baud t f(rx) fall time 10-pf load 15 % of t baud t jitter edge timing variance ? 1% 1% t w(rsl) pulse duration, reset low 250 ns t d(rsrx) delay time, start of communication after reset rising edge (or reset command decoded (1) ) tbd ns timeout (2) normal mode 32760 t mod turbo mode 65520 (1) t clk = 1 / f clk . oscillator frequency f clk = 1.024 mhz (normal mode) and 2.048 mhz (turbo mode). t mod = 1 / f mod . modulator frequency f mod = 256 khz (normal mode) and 512 khz (turbo mode). (2) the uart baud rate affects the command latch timing; see the command latching section for more details. 7.7 uart switching characteristics over operating ambient temperature range and dvdd = 2.3 v to 5.5 v (unless otherwise noted) parameter test conditions min typ max unit (1) t pd(rddr) propagation delay time, rdata command decoded to drdy rising edge (2) manual data read mode tbd t clk t pd(rdtx) propagation delay time, rdata command decoded to tx falling edge (2) manual data read mode 2 t baud t pd(drtx) propagation delay time, drdy rising edge to tx falling edge (2) automatic data read mode 2 t baud t w(drh) pulse duration, drdy high 2 t mod t w(drl) pulse duration, drdy low automatic data read mode 4 t clk t p(rreg) propagation delay time, rreg command decoded to tx falling edge (2) 2 t baud t p(gpio) propagation delay time, wreg command decoded to gpiox output valid (2) tbd tbd ns figure 1. uart timing requirements figure 2. reset pin and reset command timing requirements synchronization word reset command reset rx synchronization word new command t t d (rsrx ) t t w(rsl) rx/tx v ih v il t r(rx) t t baud t t f(rx) t t baud t t jitter t jitter advance information
10 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 3. manual data read mode drdy switching characteristics figure 4. automatic data read mode drdy switching characteristics figure 5. register read switching characteristics figure 6. gpio switching characteristics synchronization word register configuration gpiox rx wreg command t p(gpio) synchronization word tx rx rreg command t p(rreg) register data drdy tx data 1 t w(drl) t pd(drtx) synchronization word rdata command drdy rx t pd(rddr) tx data 1 t w(drh) t pd(rdtx) advance information
11 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 8 parameter measurement information 8.1 noise performance delta-sigma ( ) analog-to-digital converters (adcs) are based on the principle of oversampling. the input signal of a adc is sampled at a high frequency (modulator frequency) and subsequently filtered and decimated in the digital domain to yield a conversion result at the respective output data rate. the ratio between modulator frequency and output data rate is called oversampling ratio (osr). by increasing the osr, and thus reducing the output data rate, the noise performance of the adc can be optimized. in other words, the input- referred noise drops when reducing the output data rate because more samples of the internal modulator are averaged to yield one conversion result. increasing the gain also reduces the input-referred noise, which is particularly useful when measuring low-level signals. table 1 to table 8 summarize the device noise performance. data are representative of typical noise performance at t a = 25 c using the internal 2.048-v reference. data shown are the result of averaging readings from a single device over a time period of approximately 0.75 seconds and are measured with the inputs internally shorted together. table 1 , table 3 , table 5 , and table 7 list the input-referred noise in units of v rms for the conditions shown. values in v pp are shown in parenthesis. table 2 , table 4 , table 6 , and table 8 list the corresponding data in effective resolution calculated from v rms values using equation 1 . noise-free resolution calculated from peak-to-peak noise values using equation 2 are shown in parenthesis. the input-referred noise ( table 1 , table 3 , table 5 , and table 7 ) only changes marginally when using an external low-noise reference, such as the ref5020 . to calculate effective resolution numbers and noise-free resolution when using a reference voltage other than 2.048 v, use equation 1 and equation 2 : effective resolution = ln [2 v ref / (gain v rms-noise )] / ln(2) (1) noise-free resolution = ln [2 v ref / (gain v pp-noise )] / ln(2) (2) table 1. noise in v rms ( v pp ) at avdd = 3.3 v, avss = 0 v, normal mode, and internal reference = 2.048 v data rate (sps) gain (pga enabled) 1 2 4 8 16 32 64 128 20 3.71 (13.67) 1.54 (5.37) 1.15 (4.15) 0.80 (3.36) 0.35 (1.16) 0.23 (0.73) 0.10 (0.35) 0.09 (0.41) 45 7.36 (29.54) 2.93 (13.06) 1.71 (9.28) 0.88 (4.06) 0.50 (2.26) 0.29 (1.49) 0.19 (0.82) 0.12 (0.51) 90 10.55 (47.36) 4.50 (20.75) 2.43 (11.35) 1.51 (6.65) 0.65 (3.62) 0.42 (2.14) 0.27 (1.22) 0.18 (0.85) 175 11.90 (63.72) 6.45 (34.06) 3.26 (17.76) 1.82 (11.20) 1.01 (5.13) 0.57 (3.09) 0.34 (2.14) 0.26 (1.60) 330 19.19 (106.93) 9.38 (50.78) 4.25 (26.25) 2.68 (14.13) 1.45 (7.52) 0.79 (4.66) 0.50 (2.69) 0.34 (1.99) 600 24.78 (151.61) 13.35 (72.27) 6.68 (39.43) 3.66 (19.26) 2.10 (12.77) 1.14 (6.87) 0.70 (4.76) 0.55 (3.34) 1000 37.53 (227.29) 18.87 (122.68) 9.53 (58.53) 5.37 (31.52) 2.95 (18.08) 1.65 (10.71) 1.03 (6.52) 0.70 (4.01) table 2. effective resolution from rms noise (noise-free resolution from peak-to-peak noise) at avdd = 3.3 v, avss = 0 v, normal mode, and internal reference = 2.048 v data rate (sps) gain (pga enabled) 1 2 4 8 16 32 64 128 20 20.08 (18.19) 20.34 (18.54) 19.76 (17.91) 19.28 (17.22) 19.48 (17.75) 19.10 (17.42) 19.33 (17.49) 18.49 (16.26) 45 19.09 (17.08) 19.42 (17.26) 19.19 (16.75) 19.15 (16.94) 18.95 (16.79) 18.74 (16.39) 18.38 (16.25) 18.00 (15.49) 90 18.57 (16.40) 18.80 (16.59) 18.68 (16.46) 18.37 (16.23) 18.60 (16.11) 18.20 (15.87) 17.87 (15.67) 17.44 (15.20) 175 18.39 (15.97) 18.28 (15.88) 18.26 (15.82) 18.10 (15.48) 17.96 (15.61) 17.78 (15.34) 17.53 (14.87) 16.91 (14.29) 330 17.70 (15.23) 17.74 (15.30) 17.88 (15.25) 17.54 (15.15) 17.43 (15.05) 17.30 (14.74) 16.96 (14.54) 16.50 (13.97) 600 17.33 (14.72) 17.23 (14.79) 17.23 (14.66) 17.09 (14.70) 16.89 (14.29) 16.77 (14.18) 16.48 (13.72) 15.83 (13.23) 1000 16.74 (14.14) 16.73 (14.03) 16.71 (14.09) 16.54 (13.99) 16.41 (13.79) 16.25 (13.54) 15.92 (13.26) 15.49 (12.96) advance information
12 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated table 3. noise in v rms ( v pp ) with pga disabled at avdd = 3.3 v, avss = 0 v, normal mode, and internal reference = 2.048 v data rate (sps) gain (pga disabled) 1 2 4 20 3.89 (13.43) 1.85 (6.84) 1.26 (3.91) 45 6.97 (31.98) 2.94 (12.94) 1.41 (5.62) 90 8.50 (42.48) 4.49 (18.92) 2.07 (9.95) 175 12.99 (65.92) 6.24 (35.40) 3.04 (18.92) 330 18.18 (94.24) 8.12 (50.17) 4.71 (28.75) 600 25.29 (138.67) 12.77 (78.13) 6.27 (39.79) 1000 38.04 (260.50) 18.40 (120.97) 9.48 (63.72) table 4. effective resolution from rms noise (noise-free resolution from peak-to-peak noise) with pga disabled at avdd = 3.3 v, avss = 0 v, normal mode, and internal reference = 2.048 v data rate (sps) gain (pga disabled) 1 2 4 20 20.01 (18.22) 20.08 (18.19) 19.63 (18.00) 45 19.61 (16.97) 19.41 (17.27) 19.47 (17.48) 90 18.88 (16.56) 18.80 (16.72) 18.91 (16.65) 175 18.27 (15.92) 18.32 (15.82) 18.36 (15.72) 330 17.78 (15.41) 17.94 (15.32) 17.73 (15.12) 600 17.31 (14.85) 17.29 (14.68) 17.32 (14.65) 1000 16.72 (13.94) 16.76 (14.05) 16.72 (13.97) table 5. noise in v rms ( v pp ) at avdd = 3.3 v, avss = 0 v, turbo mode, and internal reference = 2.048 v data rate (sps) gain (pga enabled) 1 2 4 8 16 32 64 128 40 4.56 (24.17) 2.40 (11.35) 1.22 (4.94) 0.71 (2.84) 0.35 (1.60) 0.19 (0.85) 0.16 (0.71) 0.09 (0.55) 90 5.74 (25.88) 2.97 (14.40) 1.47 (5.80) 1.13 (5.52) 0.50 (2.67) 0.32 (1.32) 0.23 (1.13) 0.15 (0.69) 180 8.49 (46.88) 4.66 (21.36) 2.30 (12.88) 1.24 (7.23) 0.72 (4.82) 0.42 (2.57) 0.28 (1.47) 0.24 (1.34) 350 13.42 (84.72) 5.86 (40.04) 3.39 (19.04) 1.88 (10.13) 1.05 (6.15) 0.64 (3.59) 0.43 (2.29) 0.28 (1.39) 660 17.09 (120.36) 9.34 (47.36) 4.81 (27.83) 2.97 (17.36) 1.54 (10.21) 0.82 (4.43) 0.58 (3.67) 0.41 (2.93) 1200 25.71 (162.35) 12.31 (85.94) 6.81 (44.01) 3.72 (21.55) 2.09 (15.14) 1.23 (7.58) 0.80 (5.31) 0.57 (3.51) 2000 36.23 (265.14) 18.24 (127.32) 9.24 (65.43) 5.49 (37.02) 2.89 (18.89) 1.77 (12.00) 1.13 (7.60) 0.82 (5.81) table 6. effective resolution from rms noise (noise-free resolution from peak-to-peak noise) at avdd = 3.3 v, avss = 0 v, turbo mode, and internal reference = 2.048 v data rate (sps) gain (pga enabled) 1 2 4 8 16 32 64 128 40 19.78 (17.37) 19.71 (17.46) 19.68 (17.66) 19.45 (17.46) 19.47 (17.29) 19.37 (17.21) 18.65 (16.46) 18.40 (15.83) 90 19.45 (17.27) 19.39 (17.12) 19.41 (17.43) 18.79 (16.50) 18.97 (16.55) 18.62 (16.57) 18.11 (15.80) 17.75 (15.49) 180 18.88 (16.42) 18.75 (16.55) 18.76 (16.28) 18.65 (16.11) 18.43 (15.70) 18.23 (15.60) 17.79 (15.41) 17.05 (14.54) 350 18.22 (15.56) 18.42 (15.64) 18.21 (15.71) 18.05 (15.62) 17.89 (15.35) 17.62 (15.12) 17.20 (14.77) 16.78 (14.49) 660 17.87 (15.05) 17.74 (15.40) 17.70 (15.17) 17.39 (14.85) 17.34 (14.61) 17.25 (14.82) 16.75 (14.09) 16.25 (13.42) 1200 17.28 (14.62) 17.34 (14.54) 17.20 (14.51) 17.07 (14.54) 16.90 (14.05) 16.67 (14.04) 16.28 (13.56) 15.77 (13.15) 2000 16.79 (13.92) 16.78 (13.97) 16.76 (13.93) 16.51 (13.76) 16.44 (13.73) 16.14 (13.38) 15.79 (13.04) 15.25 (12.43) advance information
13 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated table 7. noise in v rms ( v pp ) with pga disabled at avdd = 3.3 v, avss = 0 v, turbo mode, and internal reference = 2.048 v data rate (sps) gain (pga disabled) 1 2 4 40 4.22 (22.46) 2.30 (10.74) 0.93 (3.91) 90 6.57 (31.01) 3.53 (14.28) 1.59 (6.84) 180 8.41 (55.66) 4.30 (22.09) 2.31 (14.59) 350 12.68 (75.20) 6.02 (34.18) 3.22 (17.64) 660 17.81 (111.08) 9.06 (56.76) 4.24 (27.47) 1200 25.43 (176.03) 12.70 (89.23) 6.28 (40.95) 2000 36.11 (250.98) 17.30 (131.35) 8.77 (68.18) table 8. effective resolution from rms noise (noise-free resolution from peak-to-peak noise) with pga disabled at avdd = 3.3 v, avss = 0 v, turbo mode, and internal reference = 2.048 v data rate (sps) gain (pga disabled) 1 2 4 40 19.89 (17.48) 19.76 (17.54) 20.07 (18.00) 90 19.25 (17.01) 19.15 (17.13) 19.29 (17.19) 180 18.89 (16.17) 18.86 (16.50) 18.76 (16.10) 350 18.30 (15.73) 18.38 (15.87) 18.28 (15.83) 660 17.81 (15.17) 17.79 (15.14) 17.88 (15.19) 1200 17.30 (14.51) 17.30 (14.49) 17.31 (14.61) 2000 16.79 (13.99) 16.85 (13.93) 16.83 (13.87) advance information
14 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 9 detailed description 9.1 overview the ads122u04 is a small, low-power, 24-bit, adc that offers many integrated features to reduce system cost and component count in applications measuring small sensor signals. in addition to the adc core and single-cycle settling digital filter, the device offers a low-noise, high input impedance, programmable gain amplifier (pga), an internal voltage reference, and a clock oscillator. the device also integrates a highly linear and accurate temperature sensor as well as two matched programmable current sources (idacs) for sensor excitation. all of these features are intended to reduce the required external circuitry in typical sensor applications and improve overall system performance. the device is fully configured through five registers and controlled by six commands through a universal asynchronous receiver/transmitter (uart)- compatible interface. the functional block diagram section shows the device functional block diagram. the ads122u04 adc measures a differential signal, v in , which is the difference in voltage between nodes ain p and ain n . the converter core consists of a differential, switched-capacitor, modulator followed by a digital filter. the digital filter receives a high-speed bitstream from the modulator and outputs a code proportional to the input voltage. this architecture results in a very strong attenuation of any common-mode signal. the device has two available conversion modes: single-shot conversion and continuous conversion mode. in single-shot conversion mode, the adc performs one conversion of the input signal upon request and stores the value in an internal data buffer. the device then enters a low-power state to save power. single-shot conversion mode is intended to provide significant power savings in systems that require only periodic conversions, or when there are long idle periods between conversions. in continuous conversion mode, the adc automatically begins a conversion of the input signal as soon as the previous conversion is completed. new data are available at the programmed data rate. data can be read at any time without concern of data corruption and always reflect the most recently completed conversion. 9.2 functional block diagram reference mux precision temperature sensor ain0 ain1 ain2 ain3 avdd avss dgnd refp refn 2.048-v reference 10 a to 1.5 ma mux dvdd pga 24-bit ? adc digital filter and uart interface low drift oscillator ads122u04 rx tx gpio1 gpio0 reset drdy copyright ? 2017, texas instruments incorporated advance information
15 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 9.3 feature description 9.3.1 multiplexer figure 7 shows that the device contains a very flexible input multiplexer. either four single-ended signals, two differential signals, or a combination of two single-ended signals and one differential signal can be measured. the multiplexer is configured by four bits (mux[3:0]) in the configuration register. when single-ended signals are measured, the negative adc input (ain n ) is internally connected to avss by a switch within the multiplexer. for system-monitoring purposes, the analog supply [(avdd ? avss) / 4] or the currently selected external reference voltage [(v refp ? v refn ) / 4] can be selected as inputs to the adc. the multiplexer also offers the possibility to route any of the two programmable current sources to any analog input (ainx) or to the dedicated reference pins (refp, refn). figure 7. analog input multiplexer electrostatic discharge (esd) diodes to avdd and avss protect the inputs. the absolute voltage on any input must stay within the range provided by equation 3 to prevent the esd diodes from turning on: avss ? 0.3 v < v (ainx) < avdd + 0.3 v (3) if the voltages on the input pins have any potential to violate these conditions, external schottky clamp diodes or series resistors may be required to limit the input current to safe values (see the absolute maximum ratings table). overdriving an unused input on the device can affect conversions taking place on other input pins. advance information avdd burnout current source (10 a) avss burnout current source (10 a) to adc ain p ain n ain0 ain1 avss ain2 ain3 refp refn avdd avss avdd avdd idac1 idac2 system monitors (v refp v refn ) / 4 (avdd avss) / 4 (avdd + avss) / 2 pga avdd avss avdd avss avdd avss avdd avss avdd avss
16 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) 9.3.2 low-noise programmable gain stage the device features programmable gains of 1, 2, 4, 8, 16, 32, 64, and 128. three bits (gain[2:0]) in the configuration register are used to configure the gain. gains are achieved in two stages. the first stage is a low- noise, low-drift, high input impedance, programmable gain amplifier (pga). the second gain stage is implemented by a switched-capacitor circuit at the input to the modulator. table 9 shows how each gain is implemented. table 9. gain implementation gain setting pga gain switched-capacitor gain 1 1 1 2 1 2 4 1 4 8 2 4 16 4 4 32 8 4 64 16 4 128 32 4 the pga consists of two chopper-stabilized amplifiers (a1 and a2) and a resistor feedback network that sets the pga gain. the input is equipped with an electromagnetic interference (emi) filter. figure 8 shows a simplified diagram of the pga. figure 8. simplified pga diagram v in denotes the differential input voltage v in = v ainp ? v ainn . use equation 4 to calculate the gain of the pga. gain is changed inside the device using a variable resistor, r g . pga gain = 1 + 2 r f / r g (4) the switched-capacitor gain is changed using variable capacitors at the input to the modulator. gains 1, 2, and 4 are implemented by using only the switched-capacitor circuit, which allows these gains to be used even when the pga is bypassed; see the bypassing the pga section for more information about bypassing the pga. equation 5 shows that the differential full-scale input voltage range (fsr) of the pga is defined by the gain setting and the reference voltage used: fsr = v ref / gain (5) advance information ain p 25 pf 200 r f a1 ain n 25 pf 200 r f a2 r g out p out n v in v out = pga gainv in + - + -
17 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated table 10 shows the corresponding full-scale ranges when using the internal 2.048-v reference. table 10. full-scale range gain setting fsr 1 2.048 v 2 1.024 v 4 0.512 v 8 0.256 v 16 0.128 v 32 0.064 v 64 0.032 v 128 0.016 v 9.3.2.1 pga input voltage requirements as with many amplifiers, the pga has an absolute input voltage range requirement that cannot be exceeded. the maximum and minimum absolute input voltages are limited by the voltage swing capability of the pga output. the specified minimum and maximum absolute input voltages (v ainp and v ainn ) depend on the pga gain, the maximum differential input voltage (v inmax ), and the tolerance of the analog power-supply voltages (avdd and avss). because gain on the ads122u04 is implemented by both the pga and a switched-capacitor gain circuit, there are two formulas that define the absolute input voltages. use equation 6 when the device gain is configured to less than or equal to 4. use equation 7 when the device gain is greater than 4. use the maximum differential input voltage expected in the application for v inmax . avss + 0.2 v v ainp , v ainn avdd ? 0.2 v (6) avss + 0.2 v + |v inmax | (gain ? 4) / 8 v ainp , v ainn avdd ? 0.2 v ? |v inmax | (gain ? 4) / 8 (7) figure 9 graphically shows the relationship between the pga input voltages to the pga output voltages for gains larger than 4. the pga output voltages (v outp , v outn ) depend on the pga gain and the differential input voltage magnitudes. for linear operation, the pga output voltages must not exceed avdd ? 0.2 v or avss + 0.2 v. figure 9 depicts an example of a positive differential input voltage that results in a positive differential output voltage. figure 9. pga input/output voltage relationship advance information avss avdd 0.2 v avss + 0.2 v v outp = v ainp + v in a (gain 4) / 8 v outn = v ainn v in a (gain 4) / 8 v ainn v ainp v in = v ainp v ainn pga input pga output avdd
18 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 9.3.2.2 bypassing the pga at gains of 1, 2, and 4, the device can be configured to disable and bypass the low-noise pga by setting the pga_bypass bit in the configuration register. disabling the pga lowers the overall power consumption and also removes the restrictions of equation 6 and equation 7 for the absolute input voltage range, v cm . the usable absolute input voltage range is (avss ? 0.1 v v ainp , v ainn avdd + 0.1 v) when the pga is disabled. in order to measure single-ended signals that are referenced to avss (ain p = v in , ain n = avss), the pga must be bypassed. configure the device for single-ended measurements by either connecting one of the analog inputs to avss externally or by using the internal avss connection of the multiplexer (mux[3:0] settings 1000 through 1011). when configuring the internal multiplexer for settings where ain n = avss (mux[3:0] = 1000 through 1011), the pga is automatically bypassed and disabled irrespective of the pga_bypass setting and gain is limited to 1, 2, and 4. in case gain is set to greater than 4, the device limits gain to 4. when the pga is disabled, the device uses a buffered switched-capacitor stage to obtain gains 1, 2, and 4. an internal buffer in front of the switched-capacitor stage ensures that the effect on the input loading resulting from the capacitor charging and discharging is minimal. see the electrical characteristics section for the typical values of absolute input currents (current flowing into or out of each input) and differential input currents (difference in absolute current between the positive and negative input) when the pga is disabled. for signal sources with high output impedance, external buffering may still be necessary. active buffers can introduce noise as well as offset and gain errors. consider all of these factors in high-accuracy applications. 9.3.3 modulator and internal oscillator a modulator is used in the ads122u04 to convert the analog input voltage into a pulse code modulated (pcm) data stream. the modulator runs at a modulator clock frequency of f mod = f clk / 4, where f clk is provided by the internal oscillator. the oscillator frequency, and therefore also the modulator frequency, depend on the selected operating mode. table 11 shows the oscillator and modulator frequencies for the different operating modes. table 11. oscillator and modulator clock frequencies for different operating modes operating mode f clk f mod normal mode 1.024 mhz 256 khz turbo mode 2.048 mhz 512 khz advance information
19 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 9.3.4 digital filter the device uses a linear-phase finite impulse response (fir) digital filter that performs both filtering and decimation of the digital data stream coming from the modulator. the digital filter is automatically adjusted for the different data rates and always settles within a single cycle. the frequency responses of the digital filter are illustrated in figure 10 to figure 18 for different output data rates. the filter notches and output data rate scale proportionally with the clock frequency. the internal oscillator can vary over temperature as specified in the electrical characteristics table. the data rate or conversion time, respectively, and consequently also the filter notches vary proportionally. figure 10. filter response (normal mode, dr = 20 sps) figure 11. detailed view of the filter response (normal mode, dr = 20 sps) figure 12. filter response (normal mode, dr = 45 sps) figure 13. filter response (normal mode, dr = 90 sps) frequency (hz) magnitude (db) 0 100 200 300 400 500 600 700 800 900 1000 -80 -60 -40 -20 0 d004 frequency (hz) magnitude (db) 0 20 40 60 80 100 120 140 160 180 200 -200 -160 -120 -80 -40 0 d002 frequency (hz) magnitude (db) 46 48 50 52 54 56 58 60 62 64 -200 -160 -120 -80 -40 0 d001 advance information frequency (hz) magnitude (db) 0 20 40 60 80 100 120 140 160 180 200 -80 -60 -40 -20 0 d003
20 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 14. filter response (normal mode, dr = 175 sps) figure 15. filter response (normal mode, dr = 330 sps) figure 16. filter response (normal mode, dr = 600 sps) figure 17. filter response (normal mode, dr = 1 ksps) figure 18. filter response (turbo mode, dr = 2 ksps) frequency (khz) magnitude (db) 0 1 2 3 4 5 6 7 8 9 10 -80 -60 -40 -20 0 d009 frequency (hz) magnitude (db) 0 500 1000 1500 2000 2500 3000 3500 4000 -80 -60 -40 -20 0 d007 frequency (khz) magnitude (db) 0 1 2 3 4 5 6 7 8 9 10 -80 -60 -40 -20 0 d008 frequency (hz) magnitude (db) 0 100 200 300 400 500 600 700 800 900 1000 -80 -60 -40 -20 0 d005 frequency (hz) magnitude (db) 0 200 400 600 800 1000 1200 1400 1600 1800 2000 -80 -60 -40 -20 0 d006 advance information
21 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) the first conversion starts 28.5 t clk (normal mode) or 105 t clk (turbo mode) after the start/sync command is latched. the times listed in this table do not include that time. (2) t clk = 1 / f clk . f clk = 1.024 mhz in normal mode and 2.048 mhz in turbo mode. 9.3.5 conversion times table 12 shows the actual conversion times for each data rate setting. the values provided are in terms of t clk cycles and in milliseconds. continuous conversion mode data rates are timed from one drdy falling edge to the next drdy falling edge. the first conversion starts 28.5 t clk (normal mode) or 105 t clk (turbo mode) after the start/sync command is latched. single-shot conversion mode data rates are timed from when the start/sync command is latched to the drdy falling edge and rounded to the next t clk . the exact time that a command is latched in relation to the rising edge of the stop bit depends on the baud rate; see the command latching section for details about command latch timing. table 12. conversion times nominal data rate (sps) ? 3-db bandwidth (hz) continuous conversion mode (1) single-shot conversion mode actual conversion time (t clk ) (2) actual conversion time (ms) actual conversion time (t clk ) (2) actual conversion time (ms) normal mode 20 13.1 51192 49.99 51213 50.01 45 20.0 22780 22.5 22805 22.27 90 39.6 11532 11.26 11557 11.29 175 77.8 5916 5.78 5941 5.80 330 150.1 3116 3.04 3141 3.07 600 279.0 1724 1.68 1749 1.71 1000 483.8 1036 1.01 1061 1.04 turbo mode 40 26.2 51192 25.00 51217 25.01 90 39.9 22780 11.12 22809 11.14 180 79.2 11532 5.63 11561 5.65 350 155.6 5916 2.89 5945 2.90 660 300.3 3116 1.52 3145 1.54 1200 558.1 1724 0.84 1753 0.86 2000 967.6 1036 0.51 1065 0.52 although the conversion time at the 20-sps setting is not exactly 1 / 20 hz = 50 ms, this discrepancy does not affect the 50-hz or 60-hz rejection. the conversion time and filter notches vary by the amount specified in the table for oscillator accuracy. advance information
22 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 9.3.6 voltage reference the device offers an integrated, low-drift, 2.048-v reference. for applications that require a different reference voltage value or a ratiometric measurement approach, the device offers a differential reference input pair (refp and refn). in addition, the analog supply (avdd ? avss) can be used as a reference. the reference source is selected by two bits (vref[1:0]) in the configuration register. by default, the internal reference is selected. the internal voltage reference requires less than 25 s to fully settle after power-up, when coming out of power-down mode, or when switching from an external reference source to the internal reference. the differential reference input allows freedom in the reference common-mode voltage. the reference inputs are internally buffered to increase input impedance. therefore, additional reference buffers are usually not required when using an external reference. when used in ratiometric applications, the reference inputs do not load the external circuitry; however, the analog supply current increases when using an external reference because the reference buffers are enabled. in most cases the conversion result is directly proportional to the stability of the reference source. any noise and drift of the voltage reference is reflected in the conversion result. 9.3.7 excitation current sources the device provides two matched programmable excitation current sources (idacs) for resistance temperature detector (rtd) applications. the output current of the current sources can be programmed to 10 a, 50 a, 100 a, 250 a, 500 a, 1000 a, or 1500 a using the respective bits (idac[2:0]) in the configuration register. each current source can be connected to any of the analog inputs (ainx) as well as to the dedicated reference inputs (refp and refn). both current sources can also be connected to the same pin. routing of the idacs is configured by bits (i1mux[2:0], i2mux[2:0]) in the configuration register. care must be taken not to exceed the compliance voltage of the idacs. in other words, limit the voltage on the pin where the idac is routed to (avdd ? 0.9 v), otherwise the specified accuracy of the idac current is not met. for three-wire rtd applications, the matched current sources can be used to cancel errors caused by sensor lead resistance (see the 3-wire rtd measurement section for more details). the idacs require up to 200 s to start up after the idac current is programmed to the respective value using the idac[2:0] bits. set the idac current to the respective value using the idac[2:0] bits and then select the routing for each idac (i1mux[2:0], i2mux[2:0]) thereafter. in single-shot conversion mode, the idacs remain active between any two conversions if the idac[2:0] bits are set to a value other than 000. however, the idacs are powered down whenever the powerdown command is issued. keep in mind that the analog supply current increases when enabling the idacs (that is, when the idac[2:0] bits are set to a value other than 000). the idac circuit needs this bias current to operate even when the idacs are not routed to any pin (i1mux[2:0] = i2mux[2:0] = 000). in addition, the selected output current is drawn from the analog supply when i1mux[2:0] or i2mux[2:0] are set to a value other than 000. advance information
23 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 9.3.8 sensor detection to help detect a possible sensor malfunction, the device provides internal 10- a, burn-out current sources. when enabled by setting the respective bit (bcs) in the configuration register, one current source provides current to the positive analog input (ain p ) currently selected and the other current source sinks current from the selected negative analog input (ain n ). in case of an open circuit in the sensor, these burn-out current sources pull the positive input towards avdd and the negative input towards avss, resulting in a full-scale reading. a full-scale reading can also indicate that the sensor is overloaded or that the reference voltage is absent. a near-zero reading can indicate a shorted sensor. the absolute value of the burn-out current sources typically varies by 10% and the internal multiplexer adds a small series resistance. therefore, distinguishing a shorted sensor condition from a normal reading can be difficult, especially if an rc filter is used at the inputs. in other words, even if the sensor is shorted, the voltage drop across the external filter resistance and the residual resistance of the multiplexer causes the output to read a value higher than zero. keep in mind that adc readings of a functional sensor may be corrupted when the burn-out current sources are enabled. disable the burn-out current sources when preforming the precision measurement, and only enable these sources to test for sensor fault conditions. 9.3.9 system monitor the device provides some means for monitoring the analog power supply and the external voltage reference. to select a monitoring voltage, the internal multiplexer (mux[3:0]) must be configured accordingly in the configuration register. the device automatically bypasses the pga and sets the gain to 1, irrespective of the configuration register settings when the monitoring feature is used. the system monitor function only provides a coarse result and is not meant to be a precision measurement. when measuring the analog power supply (mux[3:0] = 1101), the resulting conversion is approximately (avdd ? avss) / 4. the device uses the internal 2.048-v reference for the measurement regardless of what reference source is selected in the configuration register (vref[1:0]). when monitoring the external reference voltage source (mux[3:0] = 1100), the result is approximately (v (refp) ? v (refn) ) / 4. the device automatically uses the internal reference for the measurement. 9.3.10 offset calibration the internal multiplexer offers the option to short both pga inputs (ain p and ain n ) to mid-supply (avdd + avss) / 2. this option can be used to measure and calibrate the device offset voltage by storing the result of the shorted input voltage reading in a microcontroller and consequently subtracting the result from each following reading. take multiple readings with the inputs shorted and average the result to reduce the effect of noise. advance information
24 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 9.3.11 temperature sensor the ads122u04 offers an integrated precision temperature sensor. the temperature sensor mode is enabled by setting bit ts = 1 in the configuration register. when in temperature sensor mode, the settings of configuration register 0 have no effect and the device uses the internal reference for measurement, regardless of the selected voltage reference source. temperature readings follow the same process as the analog inputs for starting and reading conversion results. temperature data are represented as a 14-bit effective result that is left-justified within the 24-bit conversion result. data are output starting with the least significant bit (lsb). when reading the three data bytes, the last 14 bits (msbs) are used to indicate the temperature measurement result. the lsbs of the data output do not indicate temperature. only the 14 msbs are relevant. one 14-bit lsb equals 0.03125 c. negative numbers are represented in binary twos complement format. table 13 shows the mapping between temperature and digital codes. table 13. 14-bit temperature data format temperature ( c) digital output (binary) hex 128 01 0000 0000 0000 1000 127.96875 00 1111 1111 1111 0fff 100 00 1100 1000 0000 0c80 75 00 1001 0110 0000 0960 50 00 0110 0100 0000 0640 25 00 0011 0010 0000 0320 0.25 00 0000 0000 1000 0008 0.03125 00 0000 0000 0001 0001 0 00 0000 0000 0000 0000 ? 0.25 11 1111 1111 1000 3ff8 ? 25 11 1100 1110 0000 3ce0 ? 40 11 1011 0000 0000 3b00 9.3.11.1 converting from temperature to digital codes 9.3.11.1.1 for positive temperatures (for example, 50 c): twos complement is not performed on positive numbers. therefore, simply convert the number to binary code in a 14-bit, left-justified format with the msb = 0 to denote the positive sign. example: 50 c / (0.03125 c per count) = 1600 = 0640h = 00 0110 0100 0000 9.3.11.1.2 for negative temperatures (for example, ? 25 c): generate the twos complement of a negative number by complementing the absolute binary number and adding 1. then, denote the negative sign with the msb = 1. example: | ? 25 c| / (0.03125 c per count) = 800 = 0320h = 00 0011 0010 0000 twos complement format: 11 1100 1101 1111 + 1 = 11 1100 1110 0000 9.3.11.2 converting from digital codes to temperature to convert from digital codes to temperature, first check whether the msb is a 0 or a 1. if the msb is a 0, simply multiply the decimal code by 0.03125 c to obtain the result. if the msb is a 1, subtract 1 from the result and complement all bits. then, multiply the result by ? 0.03125 c. example: the device reads back 0960h: 0960h has an msb = 0. 0960h 0.03125 c = 2400 0.03125 c = 75 c example: the device reads back 3ce0h: 3ce0h has an msb = 1. subtract 1 and complement the result: 3ce0h 0320h 0320h ( ? 0.03125 c) = 800 ( ? 0.03125 c) = ? 25 c advance information
25 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 9.3.12 conversion data counter the ads122u04 offers an optional data counter word to help the host determine if the conversion data are new. the dcnt bit in the configuration register enables the conversion data counter. the data counter appears as an 8-bit word that precedes the conversion data each time a conversion result is read. the reset value of the counter is 00h. the word increments each time the adc completes a conversion. the counter rolls over to 00h after reaching ffh. when the host reads a conversion result, the host can determine if the data being read are new by comparing the counter value with the counter value obtained with the last data read. if the counter values are the same, then this result indicates that no new conversion data are available from the adc. the counter can also help the host determine if a conversion result was missed. reset the conversion data counter by clearing the dcnt bit to 0 and then setting dcnt back to 1. a device reset also resets the conversion data counter. 9.3.13 data integrity there are two methods for ensuring data integrity for data output on the ads122u04. output data can be register contents or conversion results. the data integrity modes are configured using the crc bits in the configuration register. when crc[1:0] = 01, a bitwise-inverted version of the data is output immediately following the most significant byte (msb) of the data. when crc[1:0] = 10, a 16-bit crc word is output immediately following the msb of the data. in crc mode, the checksum bytes are the 16-bit remainder of the bitwise exclusive-or (xor) of the data bytes with a crc polynomial. the crc is based on the crc-16-ccitt polynomial: x 16 + x 12 + x 5 + 1 with an initial value of ffh. the 17 binary coefficients of the polynomial are: 1 0001 0000 0010 0001. to calculate the crc, divide (xor operation) the data bytes (excluding the crc) with the polynomial and compare the calculated crc values to the adc crc value. if the values do not match, a data transmission error has occurred. in the event of a data transmission error, read the data again. the following list shows a general procedure to compute the crc value: 1. left-shift the initial data value by 16 bits, with zeros padded to the right. 2. align the msb of the crc polynomial to the left-most, logic-one value of the data. 3. perform an xor operation on the data value with the aligned crc polynomial. the xor operation creates a new, shorter-length value. the bits of the data values that are not in alignment with the crc polynomial drop down and append to the right of the new xor result. 4. when the xor result is less than 1 0000 0000 0000 0000, the procedure ends, yielding the 16-bit crc value. otherwise, continue with the xor operation shown in step 2 using the current data value. the number of loop iterations depends on the value of the initial data. 9.3.14 general-purpose digital inputs/outputs the ads122u04 offers three dedicated general-purpose input/output (gpio) pins. use the gpiondir (where n = 0, 1, 2) bits in the configuration register to configure the pin as either an input or an output. the gpiondat bits in the configuration register contain the input or output gpio data. if a gpio pin is configured as an input, the respective gpiondat bit reads the status of the pin; if the gpio pin is configured as an output, write the output status to the respective gpiondat bit. gpio2 shares a pin with the drdy signal. when the pin is configured as an output by the gpio2dir bit, the gpio2sel bit in the configuration register selects the function of the gpio2/ drdy pin. if the gpio2sel bit is cleared, gpio2 is routed to the pin. if the bit is set, the pin is driven with the drdy signal. see the configuration registers section for more information regarding the configuration of the gpio pins. advance information
26 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 9.4 device functional modes figure 19 shows a flow chart of the different operating modes and how the device transitions from one mode to another. (1) any reset (power-on, command, or pin) immediately resets the device. (2) the conversion mode is selected with the cm bit in the configuration register. (3) the powerdown command allows any ongoing conversion to complete before placing the device in power-down mode. figure 19. operating flow chart 9.4.1 power-up and reset the ads122u04 is reset in one of three ways: either by a power-on reset, by the reset pin, or by a reset command. when a reset occurs, the configuration registers reset to the default values and the device enters a low-power state. the device then waits for the start/sync command to enter conversion mode; see the uart timing requirements section for reset timing information. advance information power-on reset or reset pin high or reset command (1) low-power state reset device to default settings start/sync command? conversion mode start new conversion 1 = continuous conversion mode 0 = single-shot conversion mode no yes powerdown command? yes no power-down mode (3) powerdown command? yes no start/sync command? yes no conversion mode selection (2)
27 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated device functional modes (continued) 9.4.1.1 power-on reset when the device powers up, a reset is performed. the reset process takes approximately 50 s. after this power-up reset time, all internal circuitry (including the voltage reference) are stable and communication with the device is possible. as part of the reset process, the device sets all bits in the configuration registers to the respective default settings. by default, the device is set to single-shot conversion mode. after power-up, the device enters a low-power state. the power-up behavior is intended to prevent systems with tight power-supply requirements from encountering a current surge during power-up. 9.4.1.2 reset pin reset the adc by taking the reset pin low for a minimum of t w(rsl) and then returning the pin high. after the rising edge of the reset pin, a delay time of t d(rstx) is required before sending the first serial interface command or starting a conversion; see the uart timing requirements section for reset timing information. 9.4.1.3 reset by command reset the adc by using the reset command (06h or 07h). after the reset command is latched, a delay time of t d(rstx) is required before sending the first serial interface command or starting a conversion; see the uart timing requirements section for reset timing information. the exact time that a command is latched in relation to the rising edge of the stop bit depends on the baud rate; see the command latching section for details about command latch timing. 9.4.2 conversion modes the device operates in one of two conversion modes that are selected by the cm bit in the configuration register. these conversion modes are single-shot conversion and continuous conversion mode. a start/sync command must be issued each time the cm bit is changed. 9.4.2.1 single-shot conversion mode in single-shot conversion mode, the device only performs a conversion when a start/sync command is issued. the device consequently performs one single conversion and returns to a low-power state afterwards. the internal oscillator and all analog circuitry (except for the excitation current sources) are turned off while the device waits in this low-power state until the next conversion is started. writing to any configuration register besides register 04h when a conversion is ongoing functions as a new start/sync command that stops the current conversion and restarts a single new conversion. each conversion is fully settled (assuming the analog input signal settles to the final value before the conversion starts) because the device digital filter settles within a single cycle. 9.4.2.2 continuous conversion mode in continuous conversion mode, the device continuously performs conversions. when a conversion completes, the device places the result in the output buffer and immediately begins another conversion. in order to start continuous conversion mode, the cm bit must be set to 1 followed by a start/sync command. the first conversion starts 28.5 t clk (normal mode) or 105 t clk (turbo mode) after the start/sync command is latched. the exact time that a command is latched in relation to the rising edge of the stop bit depends on the baud rate; see the command latching section for details about command latch timing. writing to any configuration register besides register 04h during an ongoing conversion restarts the current conversion. send a start/sync command immediately after the cm bit is set to 1. stop continuous conversions by sending the powerdown command. advance information
28 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated device functional modes (continued) 9.4.3 operating modes in addition to the different conversion modes, the device can also be operated in different operating modes that can be selected to trade-off power consumption, noise performance, and output data rate. these modes are: normal mode, turbo mode, and power-down mode. 9.4.3.1 normal mode normal mode is the default mode of operation after power-up. in this mode, the internal modulator of the adc runs at a modulator clock frequency of f mod = f clk / 4 = 256 khz, where the system clock (f clk ) is provided by the internal oscillator. normal mode offers output data rate options ranging from 20 sps to 1 ksps. the data rate is selected by the dr[2:0] bits in the configuration register. 9.4.3.2 turbo mode applications that require higher data rates up to 2 ksps can operate the device in turbo mode. in this mode, the internal modulator runs at a higher frequency of f mod = f clk / 4 = 512 khz. compared to normal mode, the device power consumption increases because the modulator runs at a higher frequency. running the ads122u04 in turbo mode at a comparable output data rate as in normal mode yields better noise performance. for example, the input-referred noise at 90 sps in turbo mode is lower than the input-referred noise at 90 sps in normal mode. 9.4.3.3 power-down mode when the powerdown command is issued, the device enters power-down mode after completing the current conversion. in this mode, all analog circuitry (including the voltage reference and both idacs) are powered down and the device typically only uses 400 na of current. when in power-down mode, the device holds the configuration register settings and responds to commands, but does not perform any data conversions. issuing a start/sync command wakes up the device and either starts a single conversion or starts continuous conversion mode, depending on the conversion mode selected by the cm bit. advance information
29 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 9.5 programming 9.5.1 uart interface the serial data and control interface on the ads122u04 is universal asynchronous receiver transmitter (uart) compatible. commands from the host are received by the device through the rx pin. data are transmitted from the device to the host through the tx pin. the ads122u04 actively synchronizes to the baud rate of the host each time the host transmits a command. the interface is half duplex; meaning only either the host or the device can communicate at any given time. 9.5.1.1 receive (rx) the uart receive pin (rx) is used to send data (commands and register data) to the device. the device never drives the rx pin. 9.5.1.2 transmit (tx) the uart transmit pin (tx) is used to read conversion and register data from the device. the tx pin is held at logic high when not transmitting data. 9.5.1.3 data ready ( drdy) drdy indicates when a new conversion result is ready for retrieval. the drdy signal appears on the gpio2/ drdy pin only when gpio2 is configured as an output and the gpio2sel bit in the config4 register is set. when drdy falls low, new conversion data are ready. drdy transitions back high when the conversion result is latched for output transmission. in case a conversion result in continuous conversion mode is not read (only applies to manual data read mode), drdy pulses high for t w(drh) before the next conversion completes; see the uart switching characteristics section for more details. 9.5.1.4 protocol serial data transfer in the uart is performed in byte increments. for each byte that is sent by either the host or the device, a start bit (logic low) is transmitted first, followed by eight bits of data in lsb-first format. a stop bit (logic high) is transmitted at the end of each byte. by using a start and stop bit for each byte, the ads122u04 can latch each byte and maintain synchronous communication throughout the process. the ads122u04 actively synchronizes to the baud rate of the host each time the host transmits a command. baud rate synchronization occurs when the host transmits a synchronization word (55h) preceding any command sent to the ads122u04. the host must always transmit the synchronization word first followed by the command byte or bytes. each byte begins with a start bit and ends with a stop bit, including the synchronization word. figure 20 shows the timing sequence for the uart communication. in figure 20 , as an example, there is only one byte for the command and one byte for the readback data. there may be multiple bytes for a command or the data that is read from the device. the protocol takes the 8-n-1 format: eight (8) data bits, no (n) parity bit, and one (1) stop bit. figure 20. example ads122u04 uart protocol advance information rx tx s 1 0 1 0 1 0 1 0 p s c0 c1 c2 c3 c4 c5 c6 c7 p s d0 d1 d2 d3 d4 d5 d6 d7 p t from the host t t from the device t synchronization word command word
30 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated programming (continued) 9.5.1.5 timeout the ads122u04 offers a uart timeout feature that can be used to recover communication when a serial interface transmission is interrupted. if the host initiates contact with the ads122u04 but subsequently remains idle for 32760 t mod in normal mode and 65520 t mod in turbo mode before completing a command, the ads122u04 interface is reset. if the ads122u04 interface has reset because of a timeout condition, the host must abort the transaction and restart the communication again by sending the synchronization word first followed by the command byte or bytes. 9.5.1.6 data format the device provides 24 bits of data in binary twos complement format. use equation 8 to calculate the size of one code (lsb). 1 lsb = (2 v ref / gain) / 2 24 = +fs / 2 23 (8) a positive full-scale input [v in (+fs ? 1 lsb) = (v ref / gain ? 1 lsb)] produces an output code of 7fffffh and a negative full scale input (v in ? fs = ? v ref / gain) produces an output code of 800000h. the output clips at these codes for signals that exceed full-scale. table 14 summarizes the ideal output codes for different input signals. table 14. ideal output code versus input signal input signal, v in = v ainp ? v ainn ideal output code fs (2 23 ? 1) / 2 23 7fffffh fs / 2 23 000001h 0 000000h ? fs / 2 23 ffffffh ? fs 800000h figure 21 shows the mapping of the analog input signal to the output codes. figure 21. code transition diagram advance information 7fffffh output code - fs ? 0 ? fs input voltage v in 7ffffeh 000001h ? 000000h800000h ffffffh 800001h ? - fs 2 - 1 23 2 23 fs 2 - 1 23 2 23
31 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) operands: rrr = register address (000 to 100), x = don ' t care. 9.5.2 commands as table 15 shows, the device offers six different commands to control device operation. four commands are stand-alone instructions (reset, start/sync, powerdown, and rdata). the commands to read (rreg) and write (wreg) configuration register data from and to the device require additional information as part of the instruction. for clarity, table 15 shows the command bits msb first, but data are always transmitted byte-wise lsb first on the ads122u04. table 15. command definitions command description command byte (1) reset reset the device 0000 011x start/sync start or restart conversions 0000 100x powerdown enter power-down mode 0000 001x rdata read data by command 0001 xxxx rreg read register at address rrr 0010 rrrx wreg write register at address rrr 0100 rrrx 9.5.2.1 reset (0000 011x) resets the device to the default states. wait at least (50 s + 32 t clk ) after the reset command is sent before sending any other command. 9.5.2.2 start/sync (0000 100x) in single-shot conversion mode, the start/sync command is used to start a single conversion, or (when sent during an ongoing conversion) to reset the digital filter and then restart a single new conversion. when the device is set to continuous conversion mode, the start/sync command must be issued one time to start converting continuously. sending the start/sync command when converting in continuous conversion mode resets the digital filter and restarts continuous conversions. 9.5.2.3 powerdown (0000 001x) the powerdown command places the device into power-down mode. the command shuts down all internal analog components and turns off both idacs, but holds all register values. in case the powerdown command is issued when a conversion is ongoing, the conversion completes before the ads122u04 enters power-down mode. as soon as a start/sync command is issued, all analog components return to their previous states. 9.5.2.4 rdata (0001 xxxx) the rdata command loads the output shift register with the most recent conversion result right after the command is received. if a conversion finishes in the middle of the rdata command byte, the state of the drdy pin at the end of the read operation signals whether the old or the new result is loaded. if the old result is loaded, drdy stays low, indicating that the new result is not read out. the new conversion result loads when drdy is high. note uart transmissions take place byte-wise. bytes are transmitted least significant bit first. data words are transmitted least significant byte first. advance information
32 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 9.5.2.5 rreg (0010 rrrx) the rreg command reads the value of the register at address rrr. if the register pointed to by rrr does not exist, the read back data are 00h. figure 22 shows the sequence for reading a register. the synchronization word must be sent by the host before the rreg command is sent. figure 22. read register sequence 9.5.2.6 wreg (0100 rrrx dddd dddd) the wreg command writes dddd dddd to the register at address rrr. if the register pointed to by rrr does not exist, the wreg command is ignored. figure 23 shows the sequence for writing a register. the synchronization word must be sent by the host before the wreg command is sent. the wreg command forces the digital filter to reset and any ongoing adc conversion to restart. figure 23. write register sequence 9.5.2.7 command latching the ads122u04 interface automatically synchronizes to the baud rate of the host. this means the time required for commands to be latched by the interface varies with baud rate. commands are not processed until after being latched by the ads122u04. commands are latched by the ads122u04 when the device detects the stop bit. stop bit detection generally occurs in the middle of the stop bit where the middle of the stop bit is defined as t baud / 2 after the rising edge of the stop bit. however, this timing is not exact because of the asynchronous nature between the host baud clocking and the ads122u04 internal oscillator as well as jitter in the ads122u04 internal oscillator. the stop bit detection timing error can be as large as 4 t clk in normal mode and 8 t clk in turbo mode. 9.5.3 reading data there are two ways to read data from the ads122u04: manual data read mode and automatic data read mode. in manual data read mode, the host retrieves data by issuing the rdata command. in automatic data read mode, the ads122u04 automatically outputs conversion data on the tx pin as soon as a conversion completes. rx tx 10101010 0010 0010 reg 2h data rx tx 10101010 0010 0100 reg 2h data advance information
33 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 9.5.3.1 manual data read mode in manual data read mode, data are read by issuing the rdata command. the ads122u04 responds to the rdata command with the latest conversion data. there are three ways to monitor for new conversion data. one way is to monitor for the falling edge of the drdy signal. to configure the gpio2/ drdy pin to output the drdy signal, the pin must be configured as an output by setting the gpio2dir bit in the configuration register, and drdy must be multiplexed to the pin by setting the gpio2sel bit in the configuration register. figure 24 shows the timing diagram for collecting data in manual data read mode using drdy to indicate new data. figure 24. manual data read mode using drdy (continuous conversion mode) another way to monitor for a new conversion result is to periodically read the configuration register for the drdy bit. if set, the drdy bit indicates that a new conversion result is ready for retrieval. the host can subsequently issue an rdata command to retrieve the data. the rate at which the host polls the ads122u04 for new data must be at least as fast as the data rate in continuous conversion mode to prevent the host from missing a conversion result. if a new conversion result becomes ready during a uart transmission, the transmission will not be corrupted. the new data are loaded into the output shift register upon the following rdata command. figure 25 shows the timing diagram for collecting data in manual data read mode using the drdy bit in the configuration register to indicate new data. figure 25. manual data read mode using the rreg command (continuous conversion mode) the last way to detect if new conversion data are available is through the use of the conversion data counter word. in this mode, the host periodically requests data from the device using the rdata command and checks the conversion data counter word against the conversion data counter word read for the previous data received. if the counter values are the same, the host can disregard the data because that data has already been gathered. if the counter has incremented, the host records the data. the rate at which the host polls the ads122u04 for new data must be at least as fast as the data rate in continuous conversion mode to prevent the host from missing a conversion result. if a new conversion result becomes ready during a uart transmission, the transmission is not corrupted. the new data are loaded into the output shift register after the following rdata command. figure 26 shows the timing diagram for collecting data in manual data read mode using the conversion data counter word to indicate new data. figure 26. manual data read mode using the conversion data counter (continuous conversion mode) the conversion data counter can be used in conjunction with the previously discussed methods of detecting new data to ensure that the host did not miss a conversion result. rx tx data lsb data data msb 55h rdata counter rx tx data data msb 55h rdata data lsb 55h rreg 2h register 2h advance information drdy rx tx data lsb data data msb 55h rdata
34 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 9.5.3.2 automatic data read mode in automatic data read mode, the ads122u04 automatically outputs the latest conversion data on the tx pin without the host sending an rdata command. the drdy signal does not have to be monitored in this mode; thus making this mode useful for applications that require the number of digital lines to be minimized. using automatic data read mode requires the least amount of communication between the host and device when compared to monitoring the drdy bit of the configuration register or the conversion data counter in manual data read mode. the conversion data counter can also be used in this mode to verify that the host has not missed a conversion result. figure 27 shows the timing diagram for collecting data in automatic data read mode. figure 27. automatic data read mode (continuous conversion mode) 9.5.4 data integrity the optional data integrity checks can be configured using the crc[1:0] bits in the configuration register. when one of the data integrity options is enabled, the data integrity check is output on the tx pin immediately following the conversion data; see the data integrity section for detailed description of the data integrity functionality. additional words are always two bytes when crc16 is enabled. the number of additional words in the inverted data mode varies from three to four depending on whether the conversion data counter is enabled. figure 28 shows data retrieval in which either the inverted data or crc are enabled in the configuration register. figure 28. data output including optional data integrity bytes rx tx data lsb data data msb 55h rdata data lsb/crc0 data/crc1 data msb rx tx data0 data0 msb data0 lsb data1 data1 msb data1 lsb drdy advance information
35 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 9.6 register map 9.6.1 configuration registers the device has five 8-bit configuration registers that are accessible through the uart interface using the rreg and wreg commands. the configuration registers control how the device operates and can be changed at any time without causing data corruption. after power-up or reset, all registers are set to the default values (which are all 0). all register values are retained during power-down mode. table 16 shows the register map of the configuration registers. table 17 lists the register access codes for the ads122u04. table 16. configuration register map register (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h mux[3:0] gain[2:0] pga_bypass 01h dr[2:0] mode cm vref[1:0] ts 02h drdy dcnt crc[1:0] bcs idac[2:0] 03h i1mux[2:0] i2mux[2:0] 0 auto 04h 0 gpio2dir gpio1dir gpio0dir gpio2sel gpio2dat gpio1dat gpio0dat table 17. ads122u04 register access type codes access type code description r r read r/w r/w read-write w w write - n value after reset or the default value advance information
36 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 9.6.1.1 configuration register 0 (address = 00h) [reset = 00h] figure 29. configuration register 0 7 6 5 4 3 2 1 0 mux[3:0] gain[2:0] pga_bypass r/w-0h r/w-0h r/w-0h table 18. configuration register 0 field descriptions bit field type reset description 7:4 mux[3:0] r/w 0h input multiplexer configuration. these bits configure the input multiplexer. for settings where ain n = avss, the pga must be disabled (pga_bypass = 1) and only gains 1, 2, and 4 can be used. 0000 : ain p = ain0, ain n = ain1 (default) 0001 : ain p = ain0, ain n = ain2 0010 : ain p = ain0, ain n = ain3 0011 : ain p = ain1, ain n = ain0 0100 : ain p = ain1, ain n = ain2 0101 : ain p = ain1, ain n = ain3 0110 : ain p = ain2, ain n = ain3 0111 : ain p = ain3, ain n = ain2 1000 : ain p = ain0, ain n = avss 1001 : ain p = ain1, ain n = avss 1010 : ain p = ain2, ain n = avss 1011 : ain p = ain3, ain n = avss 1100 : (v (refp) ? v (refn) ) / 4 monitor (pga bypassed) 1101 : (avdd ? avss) / 4 monitor (pga bypassed) 1110 : ain p and ain n shorted to (avdd + avss) / 2 1111 : reserved 3:1 gain[2:0] r/w 0h gain configuration. these bits configure the device gain. gains 1, 2, and 4 can be used without the pga. in this case, gain is obtained by a switched-capacitor structure. 000 : gain = 1 (default) 001 : gain = 2 010 : gain = 4 011 : gain = 8 100 : gain = 16 101 : gain = 32 110 : gain = 64 111 : gain = 128 0 pga_bypass r/w 0h disables and bypasses the internal low-noise pga. disabling the pga reduces overall power consumption and allows the common- mode voltage range (v cm ) to span from avss ? 0.1 v to avdd + 0.1 v. the pga can only be disabled for gains 1, 2, and 4. the pga is always enabled for gain settings 8 to 128, regardless of the pga_bypass setting. 0 : pga enabled (default) 1 : pga disabled and bypassed advance information
37 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 9.6.1.2 configuration register 1 (address = 01h) [reset = 00h] figure 30. configuration register 1 7 6 5 4 3 2 1 0 dr[2:0] mode cm vref[1:0] ts r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h table 19. configuration register 1 field descriptions bit field type reset description 7:5 dr[2:0] r/w 0h data rate. these bits control the data rate setting depending on the selected operating mode. table 20 lists the bit settings for normal and turbo mode. 4 mode r/w 0h operating mode. these bits control the operating mode that the device operates in. 0 : normal mode (256-khz modulator clock, default) 1 : turbo mode (512-khz modulator clock) 3 cm r/w 0h conversion mode. this bit sets the conversion mode for the device. 0 : single-shot conversion mode (default) 1 : continuous conversion mode 2:1 vref[1:0] r/w 0h voltage reference selection. these bits select the voltage reference source that is used for the conversion. 00 : internal 2.048-v reference selected (default) 01 : external reference selected using the refp and refn inputs 10 : analog supply (avdd ? avss) used as reference 11 : analog supply (avdd ? avss) used as reference 0 ts r/w 0h temperature sensor mode. this bit enables the internal temperature sensor and puts the device in temperature sensor mode. the settings of configuration register 0 have no effect and the device uses the internal reference for measurement when temperature sensor mode is enabled. 0 : disables temperature sensor (default) 1 : enables temperature sensor table 20. dr bit settings normal mode turbo mode 000 = 20 sps 000 = 40 sps 001 = 45 sps 001 = 90 sps 010 = 90 sps 010 = 180 sps 011 = 175 sps 011 = 350 sps 100 = 330 sps 100 = 660 sps 101 = 600 sps 101 = 1200 sps 110 = 1000 sps 110 = 2000 sps 111 = reserved 111 = reserved advance information
38 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 9.6.1.3 configuration register 2 (address = 02h) [reset = 00h] figure 31. configuration register 2 7 6 5 4 3 2 1 0 drdy dcnt crc[1:0] bcs idac[2:0] r-0h r/w-0h r/w-0h r/w-0h r/w-0h table 21. configuration register 2 field descriptions bit field type reset description 7 drdy r 0h conversion result ready flag. this bit flags if a new conversion result is ready. this bit is reset when conversion data are read. 0 : no new conversion result available (default) 1 : new conversion result ready 6 dcnt r/w 0h data counter enable. the bit enables the conversion data counter. 0 : conversion counter disabled (default) 1 : conversion counter enabled 5:4 crc[1:0] r/w 0h data integrity check enable. these bits enable and select the data integrity checks. 00 : disabled (default) 01 : inverted conversion result data output enabled 10 : crc16 enabled 11 : reserved 3 bcs r/w 0h burn-out current sources. this bit controls the 10- a, burn-out current sources. the burn-out current sources can be used to detect sensor faults such as wire breaks and shorted sensors. 0 : current sources off (default) 1 : current sources on 2:0 idac[2:0] r/w 0h idac current setting. these bits set the current for both idac1 and idac2 excitation current sources. 000 : off (default) 001 : 10 a 010 : 50 a 011 : 100 a 100 : 250 a 101 : 500 a 110 : 1000 a 111 : 1500 a advance information
39 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 9.6.1.4 configuration register 3 (address = 03h) [reset = 00h] figure 32. configuration register 3 7 6 5 4 3 2 1 0 i1mux[2:0] i2mux[2:0] 0 auto r/w-0h r/w-0h r-0h r/w-0h table 22. configuration register 3 field descriptions bit field type reset description 7:5 i1mux[2:0] r/w 0h idac1 routing configuration. these bits select the channel that idac1 is routed to. 000 : idac1 disabled (default) 001 : idac1 connected to ain0 010 : idac1 connected to ain1 011 : idac1 connected to ain2 100 : idac1 connected to ain3 101 : idac1 connected to refp 110 : idac1 connected to refn 111 : reserved 4:2 i2mux[2:0] r/w 0h idac2 routing configuration. these bits select the channel that idac2 is routed to. 000 : idac2 disabled (default) 001 : idac2 connected to ain0 010 : idac2 connected to ain1 011 : idac2 connected to ain2 100 : idac2 connected to ain3 101 : idac2 connected to refp 110 : idac2 connected to refn 111 : reserved 1 reserved r 0h reserved. always write 0 0 auto r/w 0h adc data output mode. the bit controls the uart data output mode for the conversion result. 0 : manual data read (read on demand) mode (default) 1 : automatic data read mode advance information
40 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 9.6.1.5 configuration register 4 (address = 04h) [reset = 00h] figure 33. configuration register 4 7 6 5 4 3 2 1 0 0 gpio2dir gpio1dir gpio0dir gpio2sel gpio2dat gpio1dat gpio0dat r-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h table 23. configuration register 4 field descriptions bit field type reset description 7 reserved r 0h reserved. always write 0 6 gpio2dir r/w 0h gpio2 direction control. this bit configures gpio2 as an input or output. 0 : input (default) 1 : output 5 gpio1dir r/w 0h gpio1 direction control. this bit configures gpio1 as an input or output. 0 : input (default) 1 : output 4 gpio0dir r/w 0h gpio0 direction control. this bit configures gpio0 as an input or output. 0 : input (default) 1 : output 3 gpio2sel r/w 0h gpio2/ drdy control. this bit controls which source controls the state of the gpio2/ drdy pin when gpio2 is configured as an output. 0 : gpio2dat (default) 1 : drdy 2 gpio2dat r/w 0h gpio2 input/output level. this bit controls the state of gpio2 when configured as an output or holds the value of gpio2 when configured as an input. 0 : logic low (default) 1 : logic high 1 gpio1dat r/w 0h gpio1 input/output level. this bit controls the state of gpio1 when configured as an output or holds the value of gpio1 when configured as an input. 0 : logic low (default) 1 : logic high 0 gpio0dat r/w 0h gpio0 input/output level. this bit controls the state of gpio0 when configured as an output or holds the value of gpio0 when configured as an input. 0 : logic low (default) 1 : logic high advance information
41 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 10 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 10.1 application information the ads122u04 is a precision, 24-bit, delta-sigma ( ), analog-to-digital converter (adc) that offers many integrated features to ease the measurement of the most common sensor types, including various types of temperature and bridge sensors. primary considerations when designing an application with the ads122u04 include analog input filtering, establishing an appropriate external reference for ratiometric measurements, and setting the common-mode input voltage for the internal pga. connecting and configuring the serial interface appropriately is another concern. these considerations are discussed in the following sections. 10.1.1 serial interface connections figure 34 shows the principle serial interface connections for the ads122u04. figure 34. serial interface connections most microcontroller uart peripherals can operate with the ads122u04. the baud rate is determined by the host via a synchronization word that must be sent to the ads122u04 before each command. details of the uart communication protocol of the device can be found in the programming section. ti recommends placing 47- resistors in series with all digital input and output pins (tx, rx, and gpio2/ drdy). this resistance smooths sharp transitions, suppresses overshoot, and offers some overvoltage protection. care must be taken to meet all uart timing requirements because the additional resistors interact with the bus capacitances present on the digital signal lines. advance information 0.1 p f tx rx 3.3 v 47 o gpio/irq microcontroller with uart interface 0.1 p f 3.3 v dvdd dvss 47 o 47 o 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 device reset dgnd avss ain3 ain2 refn refp ain1 ain0 avdd dvdd tx rx gpio1 gpio0 0.1 p f 3.3 v 3.3 v gpio2/ drdy
42 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated application information (continued) 10.1.2 analog input filtering analog input filtering serves two purposes: first, to limit the effect of aliasing during the sampling process, and second, to reduce external noise from being a part of the measurement. as with any sampled system, aliasing can occur if proper antialias filtering is not in place. aliasing occurs when frequency components are present in the input signal that are higher than half the sampling frequency of the adc (also known as the nyquist frequency ). these frequency components are folded back and show up in the actual frequency band of interest below half the sampling frequency. inside a adc, the input signal is sampled at the modulator frequency f mod and not at the output data rate. figure 35 shows that the filter response of the digital filter repeats at multiples of the sampling frequency (f mod ). signals or noise up to a frequency where the filter response repeats are attenuated to a certain amount by the digital filter depending on the filter architecture. any frequency components present in the input signal around the modulator frequency or multiples thereof are not attenuated and alias back into the band of interest, unless attenuated by an external analog filter. figure 35. effect of aliasing advance information magnitude f mod /2 f (mod) output data rate frequency external antialiasing filter roll-off magnitude f mod /2 f (mod) output data rate frequency digital filter magnitude f mod /2 f (mod) output data rate frequency sensor signal unwanted signals unwanted signals aliasing of unwanted signals
43 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated application information (continued) many sensor signals are inherently band limited; for example, the output of a thermocouple has a limited rate of change. in this case the sensor signal does not alias back into the pass band when using a adc. however, any noise pick-up along the sensor wiring or the application circuitry can potentially alias into the pass band. power-line-cycle frequency and harmonics are one common noise source. external noise can also be generated from electromagnetic interference (emi) or radio frequency interference (rfi) sources, such as nearby motors and cellular phones. another noise source typically exists on the printed circuit board (pcb) itself in the form of clocks and other digital signals. analog input filtering helps remove unwanted signals from affecting the measurement result. a first-order resistor-capacitor (rc) filter is (in most cases) sufficient to either totally eliminate aliasing, or to reduce the effect of aliasing to a level within the noise floor of the sensor. ideally, any signal beyond f mod / 2 is attenuated to a level below the noise floor of the adc. the digital filter of the ads122u04 attenuates signals to a certain degree, as illustrated in the filter response plots in the digital filter section. in addition, noise components are usually smaller in magnitude than the actual sensor signal. therefore, using a first-order rc filter with a cutoff frequency set at the output data rate or 10 times higher is generally a good starting point for a system design. internal to the device, prior to the pga inputs, is an emi filter; see figure 8 . the cutoff frequency of this filter is approximately 31.8 mhz, which helps reject high-frequency interferences. 10.1.3 external reference and ratiometric measurements the full-scale range (fsr) of the ads122u04 is defined by the reference voltage and the pga gain (fsr = v ref / gain). an external reference can be used instead of the integrated 2.048-v reference to adapt the fsr to the specific system needs. an external reference must be used if v in is greater than 2.048 v. for example, an external 5-v reference and an avdd = 5 v are required in order to measure a single-ended signal that can swing between 0 v and 5 v. the reference inputs of the device also allow the implementation of ratiometric measurements. in a ratiometric measurement the same excitation source that is used to excite the sensor is also used to establish the reference for the adc. as an example, a simple form of a ratiometric measurement uses the same current source to excite both the resistive sensor element (such as an rtd) and another resistive reference element that is in series with the element being measured. the voltage that develops across the reference element is used as the reference source for the adc. these components cancel out in the adc transfer function because current noise and drift are common to both the sensor measurement and the reference. the output code is only a ratio of the sensor element and the value of the reference resistor. the value of the excitation current source itself is not part of the adc transfer function. 10.1.4 establishing proper limits on the absolute input voltage the ads122u04 can be used to measure various types of input signal configurations: single-ended, pseudo- differential, and fully differential signals (which can be either unipolar or bipolar). however, configuring the device properly for the respective signal type is important. signals where the negative analog input is fixed and referenced to analog ground (v ainn = 0 v) are commonly called single-ended signals . if the pga is disabled and bypassed, the absolute input voltages of the ads122u04 can be as low as 100 mv below avss and as large as 100 mv above avdd. therefore, the pga_bypass bit must be set in order to measure single-ended signals when a unipolar analog supply is used (avss = 0 v). gains of 1, 2, and 4 are still possible in this configuration. measuring a 0-ma to 20-ma or 4-ma to 20-ma signal across a load resistor of 100 referenced to gnd is a typical example. the ads122u04 can directly measure the signal across the load resistor using a unipolar supply, the internal 2.048-v reference, and gain = 1 when the pga is bypassed. if gains larger than 4 are needed to measure a single-ended signal, the pga must be enabled. in this case, a bipolar supply is required for the ads122u04 to meet the absolute input voltage requirement of the pga. signals where the negative analog input (ain n ) is fixed at a voltage other the 0 v are referred to as pseudo- differential signals . fully differential signals in contrast are defined as signals having a constant common-mode voltage where the positive and negative analog inputs swing 180 out-of-phase but have the same amplitude. advance information
44 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated application information (continued) the ads122u04 can measure pseudo-differential and fully differential signals with the pga enabled or bypassed. however, the pga must be enabled in order to use gains greater than 4. the absolute input voltages of the input signal must meet the absolute input voltage restrictions of the pga (as explained in the pga input voltage requirements section) when the pga is enabled. setting the common-mode voltage at or near (avss + avdd) / 2 in most cases satisfies the pga absolute input voltage requirements. signals where both the positive and negative inputs are always 0 v are called unipolar signals . these signals can in general be measured with the ads122u04 using a unipolar analog supply (avss = 0 v). as mentioned previously, the pga must be bypassed in order to measure single-ended, unipolar signals when using a unipolar supply. a signal is called bipolar when either the positive or negative input can swing below 0 v. a bipolar analog supply (such as avdd = 2.5 v, avss = ? 2.5 v) is required in order to measure bipolar signals with the ads122u04. a typical application task is measuring a single-ended, bipolar, 10-v signal where ain n is fixed at 0 v and ain p swings between ? 10 v and 10 v. the ads122u04 cannot directly measure this signal because the 10 v exceeds the analog power-supply limits. however, one possible solution is to use a bipolar analog supply (avdd = 2.5 v, avss = ? 2.5 v), gain = 1, and a resistor divider in front of the ads122u04. the resistor divider must divide the voltage down to 2.048 v in order to measure the voltage using the internal 2.048-v reference. 10.1.5 unused inputs and outputs to minimize leakage currents on the analog inputs, leave unused analog and reference inputs floating, or connect the inputs to mid-supply or to avdd. connecting unused analog or reference inputs to avss is possible as well, but can yield higher leakage currents on other analog inputs than the previously mentioned options. do not float unused digital inputs; excessive power-supply leakage current can result. tie all unused digital inputs to the appropriate levels, dvdd or dgnd, even when in power-down mode. connections for unused digital inputs are: ? tie the reset pin to dvdd if the reset pin is not used ? leave the gpio0 or gpio1 pins configured in the default states as gpio inputs and tie gpio0 or gpio1, respectively, to either dvdd or dgnd if unused ? leave the gpio2/ drdy pin configured in the default state as a gpio input and tie to either dvdd or dgnd if both the drdy output and gpio2 are unused advance information
45 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated application information (continued) 10.1.6 pseudo code example the following list shows a pseudo code sequence with the required steps to set up the device and the microcontroller that interfaces to the adc in order to take subsequent readings from the ads122u04 in continuous conversion mode. the dedicated gpio2/ drdy pin is used to indicate availability of new conversion data. the default configuration register settings are changed to gain = 16, continuous conversion mode. this example shows data collection using manual data read mode. power-up; delay to allow power supplies to settle and power-up reset to complete; minimum of 50 s; configure the uart interface of the microcontroller to 8-n-1 format; configure the microcontroller gpio connected to the gpio2/ drdy pin as a falling edge triggered interrupt input; send the synchronization word to the device (55h); send the reset command (06h) to make sure the device is properly reset after power-up; delay for a minimum of 50 s + 32 t clk ; write the respective register configurations with the wreg command, sending the synchronization word each time (55h, 40h, 08h, 55h, 42h, 08h, 55h, 48h, 48h); as an optional sanity check, send the synchronization word then read back all configuration registers with the rreg command (55h, 2xh); send the synchronization word to the device (55h); send the start/sync command (08h) to start converting in continuous conversion mode; loop { wait for gpio2/ drdy to transition low; send the synchronization word (55h); send the rdata command (10h); receive 3 bytes of data from tx; } send the synchronization word (55h); send the powerdown command (02h) to stop conversions and put the device in power-down mode; ti recommends running an offset calibration before performing any measurements or when changing the gain of the pga. the internal offset of the device can, for example, be measured by shorting the inputs to mid-supply (mux[3:1] = 1110). the microcontroller then takes multiple readings from the device with the inputs shorted and stores the average value in the microcontroller memory. when measuring the sensor signal, the microcontroller then subtracts the stored offset value from each device reading to obtain an offset compensated result; the offset can be either positive or negative in value. advance information
46 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 10.2 typical applications 10.2.1 k-type thermocouple measurement ( ? 200 c to +1250 c) figure 36 shows the basic connections of a thermocouple measurement system when using the internal high- precision temperature sensor for cold-junction compensation. apart from the thermocouple itself, the only external circuitry required are two biasing resistors, a simple low-pass, antialiasing filter, and the power-supply decoupling capacitors. figure 36. thermocouple measurement 10.2.1.1 design requirements (1) not accounting for error of the thermocouple and cold-junction temperature measurement; offset calibration at t (tc) = t (cj) = 25 c; no gain calibration. table 24. design requirements design parameter value supply voltage 3.3 v reference voltage internal 2.048-v reference update rate 10 readings per second thermocouple type k temperature measurement range ? 200 c to +1250 c measurement accuracy at t a = 25 c (1) 0.2 c 10.2.1.2 detailed design procedure the biasing resistors r b1 and r b2 are used to set the common-mode voltage of the thermocouple such that the input voltages do not exceed the absolute input voltage range of the pga (in this example, to mid-supply avdd / 2). if the application requires the thermocouple to be biased to gnd, either a bipolar supply (for example, avdd = 2.5 v and avss = ? 2.5 v) must be used for the device to meet the absolute input voltage requirement of the pga, or the pga must be bypassed. when choosing the values of the biasing resistors, care must be taken so that the biasing current does not degrade measurement accuracy. the biasing current flows through the thermocouple and can cause self-heating and additional voltage drops across the thermocouple leads. typical values for the biasing resistors range from 1 m to 50 m . advance information 3.3 v thermocouple c dif c cm1 c cm2 r f2 r f1 r b2 r b1 ain0 ain1 ain2 ain3 isothermal block ain p ain n low-drift oscillator reference mux precision temperature sensor rx tx avdd avss gpio1 gpio0 ti device dgnd refp refn 2.048-v reference 10 a to 1.5 ma mux dvdd pga 24-bit ? adc digital filter and uart interface 3.3 v 0.1 f 3.3 v 0.1 f copyright ? 2017, texas instruments incorporated gpio2/ reset drdy
47 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated in addition to biasing the thermocouple, r b1 and r b2 are also useful for detecting an open thermocouple lead. when one of the thermocouple leads fails open, the biasing resistors pull the analog inputs (ain0 and ain1) to avdd and avss, respectively. the adc consequently reads a full-scale value, which is outside the normal measurement range of the thermocouple voltage, to indicate this failure condition. although the device digital filter attenuates high-frequency components of noise, performance can be further improved by providing a first-order, passive rc filter at the inputs. equation 9 calculates the cutoff frequency that is created by the differential rc filter formed by r f1 , r f2 , and the differential capacitor c dif . f c = 1 / [2 (r f1 + r f2 ) c dif ] (9) two common-mode filter capacitors (c m1 and c m2 ) are also added to offer attenuation of high-frequency, common-mode noise components. choose a differential capacitor c dif that is at least an order of magnitude (10 times) larger than the common-mode capacitors (c m1 and c m2 ) because mismatches in the common-mode capacitors can convert common-mode noise into differential noise. the filter resistors r f1 and r f2 also serve as current-limiting resistors. these resistors limit the current into the analog inputs (ain0 and ain1) of the device to safe levels if an overvoltage on the inputs occur. care must be taken when choosing the filter resistor values because the input currents flowing into and out of the device cause a voltage drop across the resistors. this voltage drop shows up as an additional offset error at the adc inputs. ti therefore recommends limiting the filter resistor values to below 1 k . the filter component values used in this design are: r f1 = r f2 = 1 k , c dif = 100 nf, and c cm1 = c cm2 = 10 nf. the highest measurement resolution is achieved when matching the largest potential input signal to the fsr of the adc by choosing the highest possible gain. from the design requirement, the maximum thermocouple voltage occurs at t (tc) = 1250 c and is v (tc) = 50.644 mv as defined in the tables published by the national institute of standards and technology (nist) using a cold-junction temperature of t (cj) = 0 c. a thermocouple produces an output voltage that is proportional to the temperature difference between the thermocouple tip and the cold junction. if the cold junction is at a temperature below 0 c, the thermocouple produces a voltage larger than 50.644 mv. the isothermal block area is constrained by the operating temperature range of the device. therefore, the isothermal block temperature is limited to ? 40 c. a k-type thermocouple at t (tc) = 1250 c produces an output voltage of v (tc) = 50.644 mv ? ( ? 1.527 mv) = 52.171 mv when referenced to a cold-junction temperature of t (cj) = ? 40 c. the maximum gain that can be applied when using the internal 2.048-v reference is then calculated as (2.048 v / 52.171 mv) = 39.3. the next smaller pga gain setting that the device offers is 32. the device integrates a high-precision temperature sensor that can be used to measure the temperature of the cold junction. to measure the internal temperature of the ads122u04, the device must be set to internal temperature sensor mode by setting the ts bit to 1 in the configuration register. for best performance, careful board layout is critical to achieve good thermal conductivity between the cold junction and the device package. however, the device does not perform automatic cold-junction compensation of the thermocouple. this compensation must be done in the microcontroller that interfaces to the device. the microcontroller requests one or multiple readings of the thermocouple voltage from the device and then sets the device to internal temperature sensor mode (ts = 1) to acquire the temperature of the cold junction. an algorithm similar to the following must be implemented on the microcontroller to compensate for the cold-junction temperature: 1. measure the thermocouple voltage, v (tc) , between ain0 and ain1 2. measure the temperature of the cold junction, t (cj) , using the temperature sensor mode of the ads122u04 3. convert the cold-junction temperature into an equivalent thermoelectric voltage, v (cj) , using the tables or equations provided by nist 4. add v (tc) and v (cj) and translate the summation back into a thermocouple temperature using the nist tables or equations again in some applications, the integrated temperature sensor of the ads122u04 cannot be used (for example, if the accuracy is not high enough or if the device cannot be placed close enough to the cold junction). the additional analog input channels of the device can be used in this case to measure the cold-junction temperature with a thermistor, rtd, or an analog temperature sensor. advance information
48 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated as shown in equation 10 , the rms noise of the ads122u04 at gain = 32 and dr = 20 sps ( 0.23 v rms ) is divided by the average sensitivity of a k-type thermocouple (41 v/ c) to obtain an approximation of the achievable temperature resolution. temperature resolution = 0.23 v / 41 v/ c = 0.006 c (10) table 25 shows the register settings for this design. table 25. register settings register setting description 00h 0ah ain p = ain0, ain n = ain1, gain = 32, pga enabled 01h 08h dr = 20 sps, normal mode, continuous conversion mode 02h 00h data counter disabled, data integrity disabled, burnout current sources disabled, idacs off 03h 00h no idacs used, manual data read mode 04h 48h gpio2/ drdy pin configured as a drdy output 10.2.1.3 application curves figure 37 and figure 38 show the measurement results. the measurements are taken at t a = t (cj) = 25 c. a system offset calibration is performed at t (tc) = 25 c, which translates to a v (tc) = 0 v when t (cj) = 25 c. no gain calibration is implemented. the data in figure 37 are taken using a precision voltage source as the input signal instead of a thermocouple. the respective temperature measurement error in figure 38 is calculated from the data in figure 37 using the nist tables. the design meets the required temperature measurement accuracy given in table 24 . the measurement error shown in figure 38 does not include the error of the thermocouple itself nor the measurement error of the cold- junction temperature. those two error sources are in general larger than 0.2 c and therefore, in many cases, dominate the overall system measurement accuracy. figure 37. voltage measurement error vs v (tc) figure 38. temperature measurement error vs t (tc) temperature (c) measurement error (c) -200 0 200 400 600 800 1000 1200 -0.2 -0.1 0 0.1 0.2 d001 advance information thermocouple voltage (mv) measurement error (mv) -10 0 10 20 30 40 50 -0.01 -0.005 0 0.005 0.01 d002
49 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 10.2.2 3-wire rtd measurement ( ? 200 c to +850 c) the ads122u04 integrates all necessary features (such as dual-matched programmable current sources, buffered reference inputs, and a pga) to ease the implementation of ratiometric 2-, 3-, and 4-wire rtd measurements. figure 39 shows a typical implementation of a ratiometric 3-wire rtd measurement using the excitation current sources integrated in the device to excite the rtd as well as to implement automatic rtd lead-resistance compensation. figure 39. 3-wire rtd measurement 10.2.2.1 design requirements (1) not accounting for error of rtd; offset calibration is performed with r rtd = 100 ; no gain calibration. table 26. design requirements design parameter value supply voltage 3.3 v update rate 20 readings per second rtd type 3-wire pt100 maximum rtd lead resistance 15 rtd excitation current 500 a temperature measurement range ? 200 c to +850 c measurement accuracy at t a = 25 c (1) 0.2 c 10.2.2.2 detailed design procedure the circuit in figure 39 employs a ratiometric measurement approach. in other words, the sensor signal (that is, the voltage across the rtd in this case) and the reference voltage for the adc are derived from the same excitation source. therefore, errors resulting from temperature drift or noise of the excitation source cancel out because these errors are common to both the sensor signal and the reference. ain0 ain1 ain2 ain3 3.3 v 0.1 f 3.3 v 0.1 f c dif1 c cm1 c cm2 r f2 r f1 r ref c dif2 r lead1 r lead2 3-wire rtd r lead3 r f4 c cm4 c cm3 r f3 (idac1) (idac2) i idac1 + i idac2 ain p ain n low-drift oscillator reference mux precision temperature sensor avdd avss ti device dgnd refp refn 2.048-v reference 10 a to 1.5 ma dvdd pga 24-bit ? adc mux copyright ? 2017, texas instruments incorporated rx tx gpio1 gpio0 gpio2/drdy digital filter and uart interface reset advance information
50 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated in order to implement a ratiometric 3-wire rtd measurement using the device, idac1 is routed to one of the leads of the rtd and idac2 is routed to the second rtd lead. both currents have the same value, which is programmable by the idac[2:0] bits in the configuration register. the design of the device ensures that both idac values are closely matched, even across temperature. the sum of both currents flows through a precision, low-drift reference resistor, r ref . the voltage, v ref , generated across the reference resistor (as shown in equation 11 ) is used as the adc reference voltage. equation 11 reduces to equation 12 because i idac1 = i idac2 . v ref = (i idac1 + i idac2 ) r ref (11) v ref = 2 i idac1 r ref (12) to simplify the following discussion, the individual lead resistance values of the rtd (r leadx ) are set to zero. as equation 13 shows, only idac1 excites the rtd to produce a voltage (v rtd ) proportional to the temperature- dependable rtd value and the idac1 value. v rtd = r rtd (at temperature) i idac1 (13) the device internally amplifies the voltage across the rtd using the pga and compares the resulting voltage against the reference voltage to produce a digital output code proportional to equation 14 through equation 16 : code v rtd gain / v ref (14) code (r rtd (at temperature) i idac1 gain) / (2 i idac1 r ref ) (15) code (r rtd (at temperature) gain) / (2 r ref ) (16) as shown in equation 16 , the output code only depends on the value of the rtd, the pga gain, and the reference resistor (r ref ), but not on the idac1 value. the absolute accuracy and temperature drift of the excitation current therefore does not matter. however, because the value of the reference resistor directly affects the measurement result, choosing a reference resistor with a very low temperature coefficient is important to limit errors introduced by the temperature drift of r ref . the second idac2 is used to compensate for errors introduced by the voltage drop across the lead resistance of the rtd. all three leads of a 3-wire rtd typically have the same length and, thus, the same lead resistance. also, idac1 and idac2 have the same value. taking the lead resistance into account, use equation 17 to calculate the differential voltage (v in ) across the adc inputs (ain0 and ain1): v in = i idac1 (r rtd + r lead1 ) ? i idac2 r lead2 (17) equation 17 reduces to equation 18 when r lead1 = r lead2 and i idac1 = i idac2 : v in = i idac1 r rtd (18) in other words, the measurement error resulting from the voltage drop across the rtd lead resistance is compensated, as long as the lead resistance values and the idac values are well matched. a first-order differential and common-mode rc filter (r f1 , r f2 , c dif1 , c cm1 , and c cm2 ) is placed on the adc inputs, as well as on the reference inputs (r f3 , r f4 , c dif2 , c cm3 , and c cm4 ). the same guidelines for designing the input filter apply as described in the k-type thermocouple measurement section. match the corner frequencies of the input and reference filter for best performance. for more detailed information on matching the input and reference filter, see the rtd ratiometric measurements and filtering using the ads1148 and ads1248 application report. the reference resistor r ref not only serves to generate the reference voltage for the device, but also sets the voltages at the leads of the rtd to within the specified absolute input voltage range of the pga. when designing the circuit, care must also be taken to meet the compliance voltage requirement of the idacs. the idacs require that the maximum voltage drop developed across the current path to avss be equal to or less than avdd ? 0.9 v in order to operate accurately. this requirement means that equation 19 must be met at all times. avss + i idac1 (r lead1 + r rtd ) + (i idac1 + i idac2 ) (r lead3 + r ref ) avdd ? 0.9 v (19) the device also offers the possibility to route the idacs to the same inputs used for measurement. if the filter resistor values r f1 and r f2 in figure 39 are small enough and well matched, then idac1 can be routed to ain1 and idac2 to ain0. in this manner, even two 3-wire rtds sharing the same reference resistor can be measured with a single device. advance information
51 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated as stated in table 26 , this design example discusses the implementation of a 3-wire pt100 measurement to be used to measure temperatures ranging from ? 200 c to +850 c. the excitation current for the pt100 is chosen as i idac1 = 500 a, which means a combined current of 1 ma is flowing through the reference resistor, r ref . as mentioned previously, besides creating the reference voltage for the ads122u04, the voltage across r ref also sets the absolute input voltages for the rtd measurement. in general, choose the largest reference voltage possible that maintains the compliance voltage of the idacs and meets the absolute input voltage requirement of the pga. setting the common-mode voltage at or near half the analog supply (in this case 3.3 v / 2 = 1.65 v) in most cases satisfies the absolute input voltage requirements of the pga. equation 20 is then used to calculate the value for r ref : r ref = v ref / (i idac1 + i idac2 ) = 1.65 v / 1 ma = 1.65 k (20) the stability of r ref is critical to achieve good measurement accuracy over temperature and time. choosing a reference resistor with a temperature coefficient of 10 ppm/ c or better is advisable. if a 1.65-k value is not readily available, another value near 1.65 k (such as 1.62 k or 1.69 k ) can certainly be used as well. as a last step, the pga gain must be selected in order to match the maximum input signal to the fsr of the adc. the resistance of a pt100 increases with temperature. therefore, the maximum voltage to be measured (v inmax ) occurs at the positive temperature extreme. at 850 c, a pt100 has an equivalent resistance of approximately 391 as per the nist tables. the voltage across the pt100 equates to equation 21 : v inmax = v rtd (at 850 c) = r rtd (at 850 c) i idac1 = 391 500 a = 195.5 mv (21) the maximum gain that can be applied when using a 1.65-v reference is then calculated as (1.65 v / 195.5 mv) = 8.4. the next smaller pga gain setting available in the ads122u04 is 8. at a gain of 8, the ads122u04 offers a fsr value as described in equation 22 : fsr = v ref / gain = 1.65 v / 8 = 206.25 mv (22) this range allows for margin with respect to initial accuracy and drift of the idacs and reference resistor. after selecting the values for the idacs, r ref , and pga gain, make sure to double check that the settings meet the absolute input voltage requirements of the pga and the compliance voltage of the idacs. to determine the true absolute input voltages at the adc inputs (ain0 and ain1), the lead resistance must be taken into account as well. the smallest absolute input voltage occurs on ain0 at the lowest measurement temperature ( ? 200 c) with r leadx = 0 , and is equal to v ref = 1.65 v. the minimum absolute input voltage must not exceed the limit set in equation 7 to meet equation 23 : v ain0 (min) avss + 0.2 v + |v inmax | (gain ? 4) / 8 = 0 v + 0.2 v + 97.75 mv = 297.75 mv (23) the restriction is satisfied with v ain0 = 1.65 v. the largest absolute input voltage (calculated using equation 24 and equation 25 ) occurs on ain1 at the highest measurement temperature (850 c). v ain1 (max) = v ref + (i idac1 + i idac2 ) r lead3 + i idac1 (r lead1 + r rtd (at 850 c) ) (24) v ain1 (max) = 1.65 v + 1 ma 15 + 500 a (15 + 391 ) = 1.868 v (25) v ain1 (max) meets the requirement given by equation 7 and equates to equation 26 in this design: v ainp (max) avdd ? 0.2 v ? |v inmax | (gain ? 4) / 8 = 3.3 v ? 0.2 v ? 97.75 mv = 3.002 v (26) the restriction on the compliance voltage (avdd ? 0.9 v = 3.3 v ? 0.9 v = 2.4 v) of idac1 is met as well. table 27 shows the register settings for this design. table 27. register settings register setting description 00h 36h ain p = ain1, ain n = ain0, gain = 8, pga enabled 01h 0ah dr = 20 sps, normal mode, continuous conversion mode, external reference 02h 55h data counter disabled, data integrity disabled, burnout current sources disabled, idac = 500 a 03h 70h idac1 = ain2, idac2 = ain3, manual data read mode 04h 48h gpio2/ drdy pin configured as a drdy output advance information
52 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 10.2.2.2.1 design variations for 2-wire and 4-wire rtd measurements implementing a 2- or 4-wire rtd measurement is very similar to the 3-wire rtd measurement illustrated in figure 39 , except that only one idac is required. figure 40 shows a typical circuit implementation of a 2-wire rtd measurement. the main difference compared to a 3-wire rtd measurement is with respect to the lead resistance compensation. the voltage drop across the lead resistors, r lead1 and r lead2 , in this configuration is directly part of the measurement (as shown in equation 27 ) because there is no means to compensate the lead resistance by use of the second current source. any compensation must be done by calibration. v in = i idac1 (r lead1 + r rtd + r lead2 ) (27) figure 40. 2-wire rtd measurement figure 41 shows a typical circuit implementation of a 4-wire rtd measurement. similar to the 2-wire rtd measurement, only one idac is required for exciting and measuring a 4-wire rtd in a ratiometric manner. the main benefit of using a 4-wire rtd is that the adc inputs are connected to the rtd in the form of a kelvin connection. apart from the input leakage currents of the adc, there is no current flow through the lead resistors r lead2 and r lead3 and therefore no voltage drop is created across them. the voltage at the adc inputs consequently equals the voltage across the rtd and the lead resistance is of no concern. figure 41. 4-wire rtd measurement ain0 ain1 ain2 ain3 3.3 v 0.1 f 3.3 v 0.1 f c dif1 c cm1 c cm2 r f2 r f1 r ref c dif2 r f4 c cm4 c cm3 r f3 (idac1) i idac1 ain p ain n low-drift oscillator reference mux precision temperature sensor avdd avss ti device dgnd refp refn 2.048-v reference 10 a to 1.5 ma dvdd pga 24-bit ? adc r lead2 r lead3 4-wire rtd r lead4 r lead1 mux copyright ? 2017, texas instruments incorporated rx tx gpio1 gpio0 gpio2/drdy digital filter and uart interface reset ain0 ain1 ain2 ain3 3.3 v 0.1 f 3.3 v 0.1 f c dif1 c cm1 c cm2 r f2 r f1 r ref c dif2 r f4 c cm4 c cm3 r f3 (idac1) i idac1 ain p ain n low-drift oscillator reference mux precision temperature sensor avdd avss ti device dgnd refp refn 2.048-v reference 10 a to 1.5 ma dvdd pga 24-bit ? adc mux r lead1 r lead2 2-wire rtd copyright ? 2017, texas instruments incorporated rx tx gpio1 gpio0 gpio2/ digital filter and uart interface reset drdy advance information
53 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated as shown in equation 28 , the transfer function of a 2- and 4-wire rtd measurement differs compared to the one of a 3-wire rtd measurement by a factor of 2 because only one idac is used and only one idac flows through the reference resistor, r ref . code (r rtd (at temperature) gain) / r ref (28) in addition, the input common-mode voltage and reference voltage is reduced compared to the 3-wire rtd configuration. therefore, some further modifications may be required in case the 3-wire rtd design is used to measure 2- and 4-wire rtds as well. if the decreased absolute input voltages does not meet the minimum absolute voltage requirements of the pga anymore, either increase the value of r ref by switching in a larger resistor or, alternatively, increase the excitation current and decrease the gain at the same time. 10.2.2.3 application curves figure 42 and figure 43 show the measurement results. the measurements are taken at t a = 25 c. a system offset calibration is performed using a reference resistor of 100 . no gain calibration is implemented. the data in figure 42 are taken using precision resistors instead of a 3-wire pt100. the respective temperature measurement error in figure 43 is calculated from the data in figure 42 using the nist tables. the design meets the required temperature measurement accuracy given in table 26 . however, the measurement error shown in figure 43 does not include the error of the rtd itself. figure 42. resistance measurement error vs r rtd figure 43. temperature measurement error vs t (rtd) advance information rtd value ( : ) measurement error ( : ) 0 50 100 150 200 250 300 350 400 -0.1 -0.05 0 0.05 0.1 d003 temperature (c) measurement error (c) -200 0 200 400 600 800 1000 -0.2 -0.1 0 0.1 0.2 d004
54 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 10.2.3 resistive bridge measurement the device offers several features to ease the implementation of ratiometric bridge measurements (such as a pga with gains up to 128, buffered, and differential reference inputs). figure 44. resistive bridge measurement 10.2.3.1 design requirements table 28. design requirements design parameter value analog supply voltage 5.0 v digital supply voltage 3.3 v load cell type 4-wire load cell load cell maximum capacity 1 kg load cell sensitivity 3 mv/v excitation voltage 5 v repeatability 50 mg 10.2.3.2 detailed design procedure as shown in figure 44 , the bridge excitation voltage is simultaneously used as the reference voltage for the adc to implement a ratiometric bridge measurement. with this configuration, any drift in excitation voltage also shows up on the reference voltage, consequently canceling out drift error. either the dedicated reference inputs can be used, or the analog supply can be used as the reference if the supply is used to excite the bridge. the pga offers gains up to 128, which helps amplify the small differential bridge output signal to make optimal use of the adc full-scale range. using a symmetrical bridge with the excitation voltage equal to the supply voltage of the device ensures that the output signal of the bridge meets the absolute input voltage requirement of the pga. using a 3-mv/v load cell with a 5-v excitation yields a maximum differential voltage at the adc inputs of v inmax = 15 mv at maximum load. equation 29 then calculates the maximum gain that can be used. gain v ref / v inmax = 5 v / 15 mv = 333.3 (29) accordingly gain = 128 is used in this example. ain0 ain1 ain2 ain3 5.0 v c dif1 c cm1 c cm2 r f2 r f1 ain p ain n low-drift oscillator reference mux precision temperature sensor avdd avss ti device dgnd refp refn 2.048-v reference 10 a to 1.5 ma mux dvdd pga 24-bit ? adc 5.0 v 0.1 f 3.3 v 0.1 f copyright ? 2017, texas instruments incorporated rx tx gpio1 gpio0 gpio2/ digital filter and uart interface reset 5.0 v c dif2 drdy advance information
55 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated a first-order differential and common-mode rc filter (r f1 , r f2 , c dif1 , c cm1 , and c cm2 ) is placed on the adc inputs. the reference has an additional capacitor c dif2 to limit reference noise. care must be taken to maintain a limited amount of filtering or the measurement is no longer ratiometric. to find the repeatability of the readings, perform the following calculation. the load cell produces an output voltage of 15 mv at the maximum load of 1 kg. at a gain = 128 and dr = 20 sps the ads122u04 offers a noise-free resolution of 0.41 v pp . equation 30 then calculates the repeatability. repeatability = (1 kg / 15 mv) 0.41 v = 27 mg (30) table 29 shows the register settings for this design. table 29. register settings register setting description 00h 4eh ain p = ain1, ain n = ain2, gain = 128, pga enabled 01h 0ch dr = 20 sps, normal mode, continuous conversion mode, analog supply as reference 02h 98h data counter disabled, data integrity disabled, burnout current sources disabled, idacs off 03h 00h no idacs used, manual data read mode 04h 48h gpio2/ drdy pin configured as a drdy output advance information
56 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 11 power supply recommendations the device requires two power supplies: analog (avdd, avss) and digital (dvdd, dgnd). the analog power supply can be bipolar (for example, avdd = 2.5 v, avss = ? 2.5 v) or unipolar (for example, avdd = 3.3 v, avss = 0 v) and is independent of the digital power supply. the digital supply sets the digital i/o levels. 11.1 power-supply sequencing the power supplies can be sequenced in any order, but in no case must any analog or digital inputs exceed the respective analog or digital power-supply voltage and current limits. wait approximately 50 s after all power supplies are stabilized before communicating with the device to allow the power-up reset process to complete. 11.2 power-supply ramp rate as shown in figure 45 , the power-supply ramp rate must be monotonic and slower than 1 v per 50 s for proper device power-up over the entire temperature range. figure 45. power-supply ramp rate 11.3 power-supply decoupling good power-supply decoupling is important to achieve optimum performance. as shown in figure 46 and figure 47 , avdd, avss (when using a bipolar supply), and dvdd must be decoupled with at least a 0.1- f capacitor. place the bypass capacitors as close to the power-supply pins of the device as possible using low- impedance connections. ti recommends using multi-layer ceramic chip capacitors (mlccs) that offer low equivalent series resistance (esr) and inductance (esl) characteristics for power-supply decoupling purposes. for very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to the device pins may offer superior noise immunity. the use of multiple vias in parallel lowers the overall inductance and is beneficial for connections to ground planes. connect analog and digital grounds together as close to the device as possible. figure 46. unipolar analog power supply figure 47. bipolar analog power supply 0.1 p f 3.3 v 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 device reset dgnd avss ain3 ain2 refn refp ain1 ain0 avdd dvdd gpio2/drdy tx rx gpio1 gpio0 0.1 p f 3.3 v advance information 0.1 f 2.5 v 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 device reset dgnd avss ain3 ain2 refn refp ain1 ain0 avdd dvdd gpio2/ tx rx gpio1 gpio0 0.1 f 3.3 v 0.1 f -2.5 v drdy - 50 s - 1 v dvdd
57 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 12 layout 12.1 layout guidelines use best design practices when laying out a printed circuit board (pcb) for both analog and digital components. this recommendation generally means that the layout separates analog components [such as adcs, amplifiers, references, digital-to-analog converters (dacs), and analog muxs] from digital components [such as microcontrollers, complex programmable logic devices (cplds), field-programmable gate arrays (fpgas), radio frequency (rf) transceivers, universal serial bus (usb) transceivers, and switching regulators]. figure 48 shows an example of good component placement. although figure 48 provides a good example of component placement, the best placement for each application is unique to the geometries, components, and pcb fabrication capabilities employed. that is, there is no single layout that is perfect for every design and careful consideration must always be used when designing with any analog component. figure 48. system component placement the use of split analog and digital ground planes is not necessary for improved noise performance (although for thermal isolation this option is a worthwhile consideration). however, the use of a solid ground plane or ground fill in pcb areas with no components is essential for optimum performance. if the system being used employs a split digital and analog ground plane, ti generally recommends that the ground planes be connected together as close to the device as possible. a two-layer board is possible using common grounds for both analog and digital grounds. additional layers can be added to simplify pcb trace routing. ground fill can also reduce emi and rfi issues. ti also strongly recommends that digital components, especially rf portions, be kept as far as practically possible from analog circuitry in a given system. additionally, minimize the distance that digital control traces run through analog areas and avoid placing these traces near sensitive analog components. digital return currents usually flow through a ground path that is as close to the digital path as possible. if a solid ground connection to a plane is not available, these currents may find paths back to the source that interfere with analog performance. the implications that layout has on the temperature-sensing functions are much more significant than for adc functions. supply pins must be bypassed to ground with a low-esr ceramic capacitor. the optimum placement of the bypass capacitors is as close as possible to the supply pins. if avss is connected to a negative supply, then connect an additional bypass capacitor from avss to agnd as well. the ground-side connections of the bypass capacitors must be low-impedance connections for optimum performance. the supply current flows through the bypass capacitor terminal first and then to the supply pin to make the bypassing most effective. analog inputs with differential connections must have a capacitor placed differentially across the inputs. best input combinations for differential measurements are ain0, ain1 and ain2, ain3. the differential capacitors must be of high quality. the best ceramic chip capacitors are c0g (npo) types that have stable properties and low noise characteristics. thermally isolate a copper region around the thermocouple input connections to create a thermally-stable cold junction. obtaining acceptable performance with alternate layout schemes is possible as long as the above guidelines are followed. advance information device microcontroller signal conditioning (rc filters and amplifiers) supply generation connector or antenna ground fill or ground plane optional: split ground cut ground fill or ground plane optional: split ground cut interface transceiver ground fill or ground plane ground fill or ground plane
58 ads122u04 sbas752 ? may 2017 www.ti.com product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 12.2 layout example figure 49. layout example 9: refp 1: gpio1 8: refn 7: ain2 6: ain3 5: avss 4: dgnd 3: reset 2: gpio0 11: ain0 10: ain1 12: avdd 13: dvdd 14: gpio2/drdy 15: tx 16: rx refn refp tx gpio2/drdy ain1 ain0 avdd dvdd ain2 ain3 rx gpio1 gpio0 vias connect to either the bottom layer or an internal plane. the bottom layer or internal plane are dedicated gnd planes (gnd = dgnd = avss). reset advance information
59 ads122u04 www.ti.com sbas752 ? may 2017 product folder links: ads122u04 submit documentation feedback copyright ? 2017, texas instruments incorporated 13 device and documentation support 13.1 documentation support 13.1.1 related documentation for related documentation see the following: ? ref50xx low-noise, very low drift, precision voltage reference ? rtd ratiometric measurements and filtering using the ads1148 and ads1248 application report 13.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 13.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 13.4 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 13.5 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 13.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 14 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. advance information
package option addendum www.ti.com 26-may-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples PADS122U04IPWR preview tssop pw 16 2000 tbd call ti call ti -40 to 125 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

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